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11. 发明申请

US20150214289A1 METHODS OF FORMING SEMICONDUCTOR DEVICE INCLUDING CAPACITORS WITH MODIFIED SIDEWALLS AND RELATED DEVICES 有权
标题翻译：形成包含修改后的电容器和相关器件的电容器的半导体器件的方法
公开(公告)号：US20150214289A1
公开(公告)日：2015-07-30
申请号：US14509828
申请日：2014-10-08
申请人： Chan-Won Kim , Jung-Woo Seo , Kee-Hong Lee , Kyoung-Ryul Yoon , Seong-Kyu Yun
发明人： Chan-Won Kim , Jung-Woo Seo , Kee-Hong Lee , Kyoung-Ryul Yoon , Seong-Kyu Yun
IPC分类号： H01L49/02 , H01L21/311
CPC分类号： H01L21/311 , H01L21/31116 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L28/90
摘要： Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
摘要翻译：形成半导体器件的方法可以通过在基片上形成第一成型层并通过第一成型层形成第一孔来提供。可以在第一成型层上形成第二成型层，使得第一孔保持在第一成型层中，并且可以通过第二成型层形成第二孔以与第一孔连接。可以在第一和第二孔中形成电容器电极。

12. 发明授权

US08470663B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08470663B2
公开(公告)日：2013-06-25
申请号：US13048683
申请日：2011-03-15
申请人： Seong-Kyu Yun , Jae-Seok Kim
发明人： Seong-Kyu Yun , Jae-Seok Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31053 , H01L21/823814 , H01L21/823828 , H01L23/544 , H01L29/7848 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.
摘要翻译：制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。在集成结构上形成第一初步绝缘中间层。执行第一初步绝缘中间层的第一次抛光，直到暴露硬掩模图案的至少一个上表面，以形成第二预绝缘中间层。蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出，以形成第三初步绝缘中间层。执行硬掩模图案和第三预备绝缘中间层的第二次抛光，直到多晶硅图案暴露以形成绝缘中间层。去除多晶硅图形以形成开口。金属材料被放弃以在开口中形成栅极电极图案。

13. 发明申请

US20080247219A1 Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods 审中-公开
标题翻译：包括侧壁电阻层的电阻随机存取存储器件及相关方法
公开(公告)号：US20080247219A1
公开(公告)日：2008-10-09
申请号：US12062042
申请日：2008-04-03
申请人： Suk-Hun Choi , In-Gyu Baek , Seong-Kyu Yun , Jong-Heun Lim , Chagn-Ki Hong , Bo-Un Yoon
发明人： Suk-Hun Choi , In-Gyu Baek , Seong-Kyu Yun , Jong-Heun Lim , Chagn-Ki Hong , Bo-Un Yoon
IPC分类号： G11C11/00 , H01C17/00
CPC分类号： H01L45/04 , H01C17/06533 , H01L27/2409 , H01L27/2472 , H01L45/1233 , H01L45/146 , H01L45/1666 , Y10T29/49082
摘要： A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode. The resistive memory layer may be on side faces of the second opening and on portions of the electrode, and the second metal pattern may be in the second opening with the resistive memory layer between the second metal pattern and the side faces of the second opening and between the second metal pattern and the electrode. Related methods are also discussed.
摘要翻译：电阻随机存取存储器（RRAM）器件可以包括衬底上的第一金属图案，第一金属图案上的第一绝缘层和衬底上的第一绝缘层，电极，第一绝缘层上的第二绝缘层，电阻存储层，和第二金属图案。第一金属图案的部分可以在基板和第一绝缘层之间，并且第一绝缘层可以具有其中暴露第一金属图案的一部分的第一开口。电极可以在开口中，其中电极与第一金属图案的暴露部分电耦合。第一绝缘层可以在第二绝缘层和衬底之间，并且第二绝缘层可以具有暴露电极的一部分的第二开口。电阻性存储层可以在第二开口的侧面和电极的部分上，并且第二金属图案可以在第二开口中，第二金属图案和第二开口的侧面之间的电阻性存储层，在第二金属图案和电极之间。还讨论了相关方法。

14. 发明申请

US20110256676A1 Methods of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110256676A1
公开(公告)日：2011-10-20
申请号：US13048683
申请日：2011-03-15
申请人： Seong-Kyu Yun , Jae-Seok Kim
发明人： Seong-Kyu Yun , Jae-Seok Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31053 , H01L21/823814 , H01L21/823828 , H01L23/544 , H01L29/7848 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.
摘要翻译：制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。在集成结构上形成第一初步绝缘中间层。执行第一初步绝缘中间层的第一次抛光，直到暴露硬掩模图案的至少一个上表面，以形成第二预绝缘中间层。蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出，以形成第三初步绝缘中间层。执行硬掩模图案和第三预备绝缘中间层的第二次抛光，直到多晶硅图案暴露以形成绝缘中间层。去除多晶硅图形以形成开口。金属材料被放弃以在开口中形成栅极电极图案。

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