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    • 13. 发明授权
    • Single poly type EEPROM and method for manufacturing the EEPROM
    • 单多晶型EEPROM及其制造方法
    • US08004034B2
    • 2011-08-23
    • US12344495
    • 2008-12-27
    • Sang-Woo Nam
    • Sang-Woo Nam
    • H01L29/788H01L21/336H01L21/02
    • H01L27/11519G11C16/0433G11C2216/10H01L27/11521H01L27/11524
    • Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semiconductor substrate having an activation region and a device isolation area, not overlapping a device isolation region but overlapping only a top of the activation region. A select gate may be formed on and/or over a top of the activation region. According to embodiments, a ratio of a capacitance of a control node side to a capacitance of a bit line side may increase, which may improve a coupling ratio. According to embodiments, a junction capacitance may be maximized by not doping the floating gate with an impurity, which may allow for a reduction in chip size by securing design margins.
    • 实施例涉及单个多型式EEPROM和用于制造EEPROM的方法。 根据实施例,单个多晶型EEPROM可以包括单元电池。 单元电池可以包括形成在具有激活区域和器件隔离区域的半导体衬底之上和/或上面的控制节点的一侧的浮动栅极,其不与器件隔离区域重叠,但仅与激活区域的顶部重叠。 可以在激活区域的顶部上和/或上方形成选择栅极。 根据实施例,控制节点侧的电容与位线侧的电容的比可能增加,这可以提高耦合比。 根据实施例,通过不用杂质掺杂浮置栅极可以使结电容最大化,这可以通过确保设计余量来减小芯片尺寸。
    • 15. 发明授权
    • Apparatus and method for detecting space-time multi-user signal of base station having array antenna
    • 用于检测具有阵列天线的基站的时空多用户信号的装置和方法
    • US07623563B2
    • 2009-11-24
    • US11284688
    • 2005-11-21
    • Hye-Kyung JwaKyung ParkSeung-Chan BangYoung-Hoon KimSang-Woo Nam
    • Hye-Kyung JwaKyung ParkSeung-Chan BangYoung-Hoon KimSang-Woo Nam
    • H04B1/00
    • H04B7/0897H04B1/7103H04B1/71052H04L25/0204
    • An apparatus and method for detecting a space-time multi-user signal are disclosed. The apparatus includes: an RF/IF processing unit for converting received signals through an array antenna into digital baseband signals; a splitting unit for dividing the digital baseband signals into data signals and reference signals; a estimating unit for estimating a delay time information and a channel impulse response; a vector generating unit for receiving the reference signals and the delay time information of to thereby generate a beamforming weight vector; a matrix generating unit for receiving the channel impulse response and the beamforming weight vector to there by generate a system matrix; a filtering unit for receiving the data signals and the system matrix to multiply the system matrix to data per each antenna; a antenna combining unit for combining signals outputted from the filtering unit; and an interference cancelling unit for cancelling an interference signal.
    • 公开了一种用于检测时空多用户信号的装置和方法。 该装置包括:RF / IF处理单元,用于将通过阵列天线的接收信号转换为数字基带信号; 分割单元,用于将数字基带信号分割成数据信号和参考信号; 用于估计延迟时间信息和信道脉冲响应的估计单元; 矢量生成单元,用于接收参考信号和延迟时间信息,从而生成波束形成权重向量; 矩阵生成单元,用于通过生成系统矩阵来接收信道脉冲响应和波束成形权重向量到达那里; 用于接收数据信号和系统矩阵的滤波单元,以将系统矩阵乘以每个天线的数据; 天线组合单元,用于组合从所述滤波单元输出的信号; 以及用于消除干扰信号的干扰消除单元。
    • 16. 发明授权
    • Method of fabricating flash memory device with increased coupling ratio
    • 具有增加耦合比的闪存器件的制造方法
    • US07618863B2
    • 2009-11-17
    • US11849673
    • 2007-09-04
    • Sang-Woo Nam
    • Sang-Woo Nam
    • H01L29/788
    • H01L29/42324H01L27/115H01L27/11521
    • A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.
    • 一种制造闪速存储器的方法,其增加了单元中的浮动栅极和控制栅极之间的耦合比。 该方法包括在半导体衬底的有源区上依次形成隧道氧化物膜和用于浮置栅极的多晶硅和第一绝缘膜; 在所述第一绝缘膜上形成作为掩模的光致抗蚀剂,并且使用所述光致抗蚀剂作为掩模进行蚀刻处理; 通过在半导体衬底上沉积防止氧化的第二绝缘膜来形成硬掩模; 通过使用硬掩模形成STI; STI的氧化侧壁和填充STI的间隙; 通过去除剩余的作为硬掩模的第二绝缘膜形成浮栅; 并在浮栅上依次形成ONO膜和控制栅。
    • 18. 发明申请
    • METHOD OF FABRICATING FLASH MEMORY DEVICE
    • 制造闪存存储器件的方法
    • US20080054344A1
    • 2008-03-06
    • US11849673
    • 2007-09-04
    • Sang-Woo Nam
    • Sang-Woo Nam
    • H01L29/788H01L21/336
    • H01L29/42324H01L27/115H01L27/11521
    • A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.
    • 一种制造闪速存储器的方法,其增加了单元中的浮动栅极和控制栅极之间的耦合比。 该方法包括在半导体衬底的有源区上依次形成隧道氧化物膜和用于浮置栅极的多晶硅和第一绝缘膜; 在所述第一绝缘膜上形成作为掩模的光致抗蚀剂,并且使用所述光致抗蚀剂作为掩模进行蚀刻处理; 通过在半导体衬底上沉积防止氧化的第二绝缘膜来形成硬掩模; 通过使用硬掩模形成STI; STI的氧化侧壁和填充STI的间隙; 通过去除剩余的作为硬掩模的第二绝缘膜形成浮栅; 并在浮栅上依次形成ONO膜和控制栅。
    • 19. 发明申请
    • METHOD OF FABRICATING FLASH MEMORY DEVICE
    • 制造闪存存储器件的方法
    • US20100019307A1
    • 2010-01-28
    • US12572912
    • 2009-10-02
    • Sang-Woo Nam
    • Sang-Woo Nam
    • H01L29/788H01L21/28
    • H01L29/42324H01L27/115H01L27/11521
    • A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.
    • 一种制造闪速存储器的方法,其增加了单元中的浮动栅极和控制栅极之间的耦合比。 该方法包括在半导体衬底的有源区上依次形成隧道氧化物膜和用于浮置栅极的多晶硅和第一绝缘膜; 在所述第一绝缘膜上形成作为掩模的光致抗蚀剂,并且使用所述光致抗蚀剂作为掩模进行蚀刻处理; 通过在半导体衬底上沉积防止氧化的第二绝缘膜来形成硬掩模; 通过使用硬掩模形成STI; STI的氧化侧壁和填充STI的间隙; 通过去除剩余的作为硬掩模的第二绝缘膜形成浮栅; 并在浮栅上依次形成ONO膜和控制栅。