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    • 12. 发明授权
    • Clock synchronization method
    • 时钟同步方式
    • US06337891B1
    • 2002-01-08
    • US09216838
    • 1998-12-21
    • Joo Yong Kim
    • Joo Yong Kim
    • H03D324
    • H04L7/033H03L7/085H03L7/093H03L7/191
    • A clock synchronization method, for use in generating a system clock of a predetermined frequency with reference to a reference clock, receives the reference clock, the system clock and a divided clock having a same frequency as that of the reference clock, wherein the divided clock is obtained by dividing the system clock by a predetermined integer. Phase deviations between the reference clock and the divided clock are obtained, wherein a phase deviation is the number of periods of the system clock in a section between a rising edge of the reference clock and a nearest rising edge of the divided clock. Consecutive phase deviations are averaged to thereby generate an average phase deviation of a 3rd order, wherein the number of averaged consecutive phase deviations varies according to phase jitter characteristics of the reference clock. And, the frequency of the system clock is controlled based on the average phase deviation of the 3rd order.
    • 用于参考参考时钟产生预定频率的系统时钟的时钟同步方法接收参考时钟,系统时钟和具有与参考时钟相同频率的分频时钟,其中分频时钟 通过将系统时钟除以预定的整数而获得。 获得参考时钟和分频时钟之间的相位偏差,其中相位偏差是参考时钟的上升沿与分频时钟的最近上升沿之间的一段中的系统时钟的周期数。 对连续的相位偏差进行平均,从而产生三阶平均相位偏差,其中平均连续相位偏移的数量根据参考时钟的相位抖动特性而变化。 而且,系统时钟频率是根据三阶平均相位偏差来控制的。