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11. 发明授权

US07313723B2 Self-reparable semiconductor and method thereof 有权
标题翻译：自修复半导体及其方法
公开(公告)号：US07313723B2
公开(公告)日：2007-12-25
申请号：US11594312
申请日：2006-11-08
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F11/00
CPC分类号： H01L22/22 , G06F11/2028 , G06F11/2038 , G06F11/2051 , G11C29/848 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor comprises first and second physical layer devices each including first and second subfunctional units that cooperate to provide first and second ports associated with a multi-bit Gigabit physical layer device. A first spare physical layer device includes first and second subfunctional units. The first sub-functional units are functionally interchangeable. The second sub-functional units are functionally interchangeable. Switching devices communicate with the first and second subfunctional units of the first, second and first spare physical layer devices and replace at least one of the first and second sub-functional units of at least one of the first and second physical layer devices with at least one of the first and second sub-functional units of the first spare physical layer device when the at least one of the first and second sub-functional units is non-operable.
摘要翻译：自修复半导体包括第一和第二物理层设备，每个物理层设备包括协作以提供与多比特千兆位物理层设备相关联的第一和第二端口的第一和第二子功能单元。第一备用物理层设备包括第一和第二子功能单元。第一个子功能单元在功能上是可互换的。第二子功能单元在功能上是可互换的。交换设备与第一，第二和第一备用物理层设备的第一和第二子功能单元通信，并且至少替换第一和第二物理层设备中的至少一个的第一和第二子功能单元中的至少一个，当第一和第二子功能单元中的至少一个不可操作时，第一备用物理层设备的第一和第二子功能单元之一。

12. 发明授权

US07185225B2 Self-reparable semiconductor and method thereof 有权
标题翻译：自修复半导体及其方法
公开(公告)号：US07185225B2
公开(公告)日：2007-02-27
申请号：US10358709
申请日：2003-02-05
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F11/00
CPC分类号： H01L22/22 , G06F11/2028 , G06F11/2038 , G06F11/2051 , G11C29/848 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually.
摘要翻译：自修复半导体包括执行相同功能并且包括子功能单元的多个功能单元。半导体包括集成到半导体中的一个或多个全部或部分备用功能单元。如果检测到子功能单元中的缺陷，那么该子功能单元被切换并且被全部或部分备用功能单元中的子功能单元替换。通过与子功能单元相关联的开关设备来实现重新配置。可以在组装，上电，定期运行和/或手动期间检测功能或子功能单元的不良。

13. 发明授权

US5764718A Ripple carry logic ASND method 失效
标题翻译：纹波进位逻辑ASND方法
公开(公告)号：US5764718A
公开(公告)日：1998-06-09
申请号：US847933
申请日：1997-04-28
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G11C19/00 , G11C21/00
CPC分类号： G11C21/005 , G11C19/00
摘要： Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval, and carry output signals from preceding logic stages are supplied to carry inputs of successive logic stages without additional delays following the processing delay interval of each preceding logic stage.
摘要翻译：用于逻辑地处理表示多位数位的多位的信号的装置和方法包括：将输入寄存器之间的延迟间隔连续地延迟从相关联的输入寄存器到逻辑处理级的应用，该延迟间隔基本上等于处理延迟间隔每个位级处理阶段。以这种方式，在逻辑处理的多个数字中的每一个的连续更多有效位有效地可用于在基本上等于先前位级逻辑级的处理延迟间隔的延迟之后的每个位级逻辑级处理。类似地，用于锁存每个位级逻辑级的逻辑输出的输出寄存器以基本上等于处理延迟间隔的连续延迟的时间间隔进行计时，并且提供来自先前逻辑级的进位输出信号以提供连续逻辑级的输入，而无需额外的延迟遵循每个前一逻辑级的处理延迟间隔。

14. 再颁专利

USRE41792E1 Controllable integrator 有权
标题翻译：可控积分器
公开(公告)号：USRE41792E1
公开(公告)日：2010-10-05
申请号：US10614084
申请日：2003-07-08
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F7/64 , H03F1/04
CPC分类号： G06G7/184 , H03G1/0029 , H03G5/10
摘要： Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.
摘要翻译：用于选择性地引入电容和用于控制一个或多个放大器的跨导传递函数的集成电路包括具有一对或多对差分放大器的差分放大器的一对或多对可切换电容性组件的级联差分放大器，以便于在宽范围的工作频率下进行操作控制外部信号。

15. 发明申请

US20070055907A1 Self-reparable semiconductor and method thereof 有权
标题翻译：自修复半导体及其方法
公开(公告)号：US20070055907A1
公开(公告)日：2007-03-08
申请号：US11594537
申请日：2006-11-08
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F11/00
CPC分类号： H01L22/22 , G06F11/2028 , G06F11/2038 , G06F11/2051 , G11C29/848 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor comprises M functional units each including N sub-functional units. Corresponding ones of the N sub-functional units in each of the M functional units perform the same function. At least two of the N sub-functional units in one of the M functional units perform different functions. A first spare functional unit includes X sub-functional units, wherein X is greater than or equal to one and less than or equal to N and wherein the X sub-functional units of. the first spare functional unit are functionally interchangeable with corresponding sub-functional units of the M functional units and wherein the X sub-functional units are provided for the at least two of the N sub-functional units. A plurality of switching devices replace at least one of the N sub-functional units with at least one of the X sub-functional units when the at least one of the N sub-functional units is non-operable.
摘要翻译：自修复半导体包括各自包括N个子功能单元的M个功能单元。每个M个功能单元中的N个子功能单元中的相应的功能单元执行相同的功能。 M个功能单元之一中的N个子功能单元中的至少两个执行不同的功能。第一备用功能单元包括X个子功能单元，其中X大于或等于1且小于或等于N，并且其中X个子功能单元。第一备用功能单元与功能单元的相应子功能单元功能上可互换，并且其中为N个子功能单元中的至少两个提供了X个子功能单元。当N个子功能单元中的至少一个不可操作时，多个交换设备用至少一个X子功能单元替换N个子功能单元中的至少一个。

16. 发明申请

US20060001669A1 Self-reparable semiconductor and method thereof 审中-公开
标题翻译：自修复半导体及其方法
公开(公告)号：US20060001669A1
公开(公告)日：2006-01-05
申请号：US11196651
申请日：2005-08-03
申请人： Sehat Sutardja , Pantas Sutardja , William Lo
发明人： Sehat Sutardja , Pantas Sutardja , William Lo
IPC分类号： G06F15/16
CPC分类号： G06F11/2033 , G01R31/318536 , G06F11/2007 , G06F11/2038 , G06F11/2041 , G11C29/848 , H01L27/14603
摘要： A self-reparable semiconductor including a graphics processing unit includes a first pixel processor that performs a first function and a first spare pixel processor. The first and first spare pixel processors are functionally interchangeable. Switching devices communicate with the first and first spare pixel processors and replace the first pixel processor with the first spare pixel processor when the first pixel processor is inoperable. A controller identifies at least one inoperable pixel processor and generates configuration data for configuring the switching devices to replace the inoperable pixel processor. Memory that is located on the self-reparable semiconductor stores the configuration data for the switching devices. A second pixel processor is functionally interchangeable with the first and first spare pixel processors. The first spare pixel processor is located one of between the first and second pixel processors or adjacent to one of the first or the second pixel processors.
摘要翻译：包括图形处理单元的自修复半导体包括执行第一功能的第一像素处理器和第一备用像素处理器。第一和第一备用像素处理器在功能上是可互换的。当第一像素处理器不可操作时，开关装置与第一和第一备用像素处理器进行通信，并用第一备用像素处理器替换第一像素处理器。控制器识别至少一个不可操作的像素处理器，并且生成用于配置切换装置以替换不可操作的像素处理器的配置数据。位于自修复半导体的存储器存储开关器件的配置数据。第二像素处理器在功能上可与第一和第一备用像素处理器互换。第一备用像素处理器位于第一和第二像素处理器之一之间或与第一或第二像素处理器之一相邻。

17. 再颁专利

USRE37739E1 Controllable integrator 有权
标题翻译：可控积分器
公开(公告)号：USRE37739E1
公开(公告)日：2002-06-11
申请号：US09609007
申请日：2000-06-22
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06G764
CPC分类号： G06G7/184 , H03G1/0029 , H03G5/10
摘要： Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.
摘要翻译：用于选择性地引入电容和用于控制一个或多个放大器的跨导传递函数的集成电路包括具有一对或多对差分放大器的差分放大器的一对或多对可切换电容性组件的级联差分放大器，以便于在宽范围的工作频率下进行操作控制外部信号。

18. 再颁专利

USRE37716E1 High-speed, low power, medium resolution analog-to-digital converter and method of stabilization 有权
标题翻译：高速，低功耗，中分辨率模数转换器和稳定方法
公开(公告)号：USRE37716E1
公开(公告)日：2002-05-28
申请号：US09760705
申请日：2001-01-17
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： H03M110
CPC分类号： H03M1/1061 , H03M1/365
摘要： A full flash analog to digital converter operates on an input voltage with a track/hold circuit coupled to a reference input of each of multiple comparators. Particular track/hold circuits are activated in sequence through a track/hold select circuit, and a look-up table and a digital-to-analog converter are coupled to supply corrected reference voltages to each track/hold circuit. Outputs of the comparators are supplied to a decoder which produces the digital output representative of the input voltage. The converter is calibrated before it is used for conversion by sensing the input offset voltages of each of the comparators and by altering the reference voltage for each comparator to produce a calibrated reference voltage for each comparator. A digital representation of the calibrated reference voltage for each comparator is stored in a look-up table for retrieval as needed to supply to a particular track/hold circuit a corresponding calibrated analog reference voltage for a particular comparator. Digital representations in the look-up table may indicate switch settings required to provide corrected reference voltages, or may indicate the required corrected reference voltage that is supplied by digital to analog converter which converts the digital representation into an analog corrected reference voltage that is held by the track/hold circuit. In this manner, each track/hold circuit is loaded with its respective calibrated reference voltage. An input signal applied to each comparator triggers such comparators upon parity between the corrected reference voltage and input voltage, and all comparator outputs are supplied to a decoder which produces a digital representation of the input signal. Occasionally, the entries in the look-up table and each track/hold circuit may be refreshed or updated in order to compensate for drift of the calibrated reference voltage.
摘要翻译：全闪存模数转换器对输入电压进行操作，其中跟踪/保持电路耦合到多个比较器中的每一个的参考输入。特定的轨道/保持电路通过轨道/保持选择电路依次被激活，并且查找表和数模转换器被耦合以向每个轨道/保持电路提供校正的参考电压。比较器的输出被提供给产生代表输入电压的数字输出的解码器。转换器在通过感测每个比较器的输入偏移电压并通过改变每个比较器的参考电压而被用于转换之前进行校准，以产生每个比较器的校准参考电压。每个比较器的校准参考电压的数字表示被存储在查找表中，以便根据需要提供给特定的跟踪/保持电路用于特定比较器的对应的校准模拟参考电压。查找表中的数字表示可以指示提供校正的参考电压所需的开关设置，或者可以指示由数模转换器提供的所需的校正参考电压，该数模转换器将数字表示转换成模拟校正参考电压，该参考电压由轨道/保持电路。以这种方式，每个轨道/保持电路装载其相应的校准参考电压。施加到每个比较器的输入信号在校正的参考电压和输入电压之间的奇偶校验器上触发这样的比较器，并且所有比较器输出被提供给产生输入信号的数字表示的解码器。偶尔地，可以刷新或更新查找表和每个跟踪/保持电路中的条目，以补偿校准的参考电压的漂移。

19. 发明授权

US5805006A Controllable integrator 失效
公开(公告)号：US5805006A
公开(公告)日：1998-09-08
申请号：US848549
申请日：1997-04-28
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06G7/184 , H03G1/00 , H03G5/10 , G06G7/64
CPC分类号： G06G7/184 , H03G1/0029 , H03G5/10
摘要： Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.

20. 发明申请

US20110163728A1 POWER MANAGEMENT CIRCUIT OF RECHARGEABLE BATTERY STACK 有权
标题翻译：可充电电池堆的电源管理电路
公开(公告)号：US20110163728A1
公开(公告)日：2011-07-07
申请号：US12973298
申请日：2010-12-20
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： H02J7/06
CPC分类号： H02J7/0014 , H02J7/0016 , H02J7/0026 , H02J7/345 , Y02T10/7055
摘要： A system includes a sensing module and a switching module. The sensing module is configured to sense output voltages of first and second cells connected in series in a rechargeable battery stack. The switching module is configured to alternately connect a capacitance across the first cell and the second cell at a switching frequency when a difference in the output voltages is greater than or equal to a first threshold. The switching module is further configured to stop alternately connecting the capacitance when the difference is less than or equal to a second threshold, wherein the first threshold is greater than the second threshold.
摘要翻译：系统包括感测模块和开关模块。感测模块被配置为感测串联连接在可充电电池组中的第一和第二电池的输出电压。开关模块被配置为当输出电压的差大于或等于第一阈值时，以开关频率在第一单元和第二单元之间交替连接电容。所述切换模块还被配置为当所述差小于或等于第二阈值时停止交替地连接所述电容，其中所述第一阈值大于所述第二阈值。

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