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11. 发明授权

US07408829B2 Methods and arrangements for enhancing power management systems in integrated circuits 有权
标题翻译：集成电路中增强电源管理系统的方法和安排
公开(公告)号：US07408829B2
公开(公告)日：2008-08-05
申请号：US11352699
申请日：2006-02-13
申请人： Jente B. Kuang , Hung Cai Ngo
发明人： Jente B. Kuang , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要翻译：本文提供了为集成电路配置电源管理系统的方法和布置。功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

12. 发明申请

US20080130387A1 METHOD FOR EVALUATING MEMORY CELL PERFORMANCE 失效
标题翻译：评估记忆体性能的方法
公开(公告)号：US20080130387A1
公开(公告)日：2008-06-05
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

13. 发明授权

US08208339B2 Computer program product for controlling a storage device having per-element selectable power supply voltages 有权
标题翻译：用于控制具有每元件可选电源电压的存储装置的计算机程序产品
公开(公告)号：US08208339B2
公开(公告)日：2012-06-26
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

14. 发明授权

US07733720B2 Method and system for determining element voltage selection control values for a storage device 失效
标题翻译：用于确定存储设备的元件电压选择控制值的方法和系统
公开(公告)号：US07733720B2
公开(公告)日：2010-06-08
申请号：US11941161
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C11/41 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/72
摘要： A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.
摘要翻译：用于确定存储设备的元件电压选择控制值的方法和系统在保持特定性能水平的同时在存储阵列中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。在测试时间，除非要求该元件满足性能要求，否则需要为虚拟电源轨设置最小电源电压的每个元件的选择电路确定数字控制值。然后可以将该组数字控制值编程为保险丝或用于在制造时调整掩模，或者与存储设备一起提供在介质上并在系统初始化时加载到设备中。

15. 发明申请

US20090172451A1 METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有全元选择电源电压的存储设备的方法和计算机程序
公开(公告)号：US20090172451A1
公开(公告)日：2009-07-02
申请号：US12399551
申请日：2009-03-06
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非该元件需要较高的电源电压以满足性能要求。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

16. 发明申请

US20090016141A1 Methods and Arrangements for Enhancing Power Management Systems in Integrated Circuits 有权
标题翻译：集成电路中增强电源管理系统的方法与安排
公开(公告)号：US20090016141A1
公开(公告)日：2009-01-15
申请号：US12099913
申请日：2008-04-09
申请人： Jente B. Kuang , Hung Cai Ngo
发明人： Jente B. Kuang , Hung Cai Ngo
IPC分类号： G05F1/10 , G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要翻译：本文提供了为集成电路配置电源管理系统的方法和布置。功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

17. 发明授权

US07349271B2 Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance 有权
标题翻译：级联测试电路采用位线驱动器件，用于评估存储单元性能
公开(公告)号：US07349271B2
公开(公告)日：2008-03-25
申请号：US11250061
申请日：2005-10-13
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：具有用于评估存储器单元性能的位线驱动装置的级联测试电路在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者可以响应于级联头部引入的转换来测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

18. 发明授权

US06566921B1 Apparatus and method for high resolution frequency adjustment in a multistage frequency synthesizer 失效
标题翻译：用于多级频率合成器中高分辨率频率调整的装置和方法
公开(公告)号：US06566921B1
公开(公告)日：2003-05-20
申请号：US09631718
申请日：2000-08-03
申请人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
发明人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
IPC分类号： H03L706
CPC分类号： H03L7/23
摘要： An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.
摘要翻译：一种用于在多级频率合成器中进行高分辨率频率调整的装置和方法。频率合成器的初始阶段是连接到动态可变分频器的常规锁相环。存在一个或多个中间级，其包括通过固定分频器反馈并连接到动态可变分频器的锁相环的前部。最后一个阶段包括通过固定分频器反馈并连接到另一个固定分频器的锁相环的前向部分。通过改变电路中可变分频器的分频常数，可以非常快速地进行微调频率调整。调整精度取决于分频器的相对值和系统中的中间级数。

19. 发明授权

US06393446B1 32-bit and 64-bit dual mode rotator 失效
标题翻译： 32位和64位双模旋转器
公开(公告)号：US06393446B1
公开(公告)日：2002-05-21
申请号：US09343450
申请日：1999-06-30
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Joel Abraham Silberman
IPC分类号： G06F700
CPC分类号： G06F7/762 , G06F5/015
摘要： A dual mode rotator capable of performing 32-bit and 64-bit rotation. According to a preferred embodiment, the dual mode rotator includes a first, second, and third rotator units wherein each rotator has a plurality of inputs and outputs. The inputs of the second rotator are operatively connected to the corresponding outputs of the first rotator unit. The inputs of the third rotator unit are operatively connected to the corresponding outputs of the second rotator. Responsive to selection of 32-bit rotation mode, the upper half of the inputs to the first rotator are zero and the lower half of the outputs of the third rotator are replicated in the upper half of the outputs of the third rotator.
摘要翻译：能够执行32位和64位旋转的双模旋转器。根据优选实施例，双模旋转器包括第一，第二和第三旋转单元，其中每个旋转器具有多个输入和输出。第二旋转器的输入可操作地连接到第一旋转单元的相应输出端。第三旋转单元的输入可操作地连接到第二旋转器的相应输出。响应于选择32位旋转模式，第一旋转器的输入的上半部分为零，并且第三旋转器的输出的下半部分被复制在第三旋转器的输出的上半部分中。

20. 发明授权

US06360238B1 Leading zero/one anticipator having an integrated sign selector 失效
标题翻译：领先的零/一个预测器具有集成的符号选择器
公开(公告)号：US06360238B1
公开(公告)日：2002-03-19
申请号：US09270469
申请日：1999-03-15
申请人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F501
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.
摘要翻译：公开了具有集成符号选择器的零/一预测器。通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。前导零字符串为正和，前导字符串为负数。然后从前导零字符串和前导字符串确定归一化偏移量。然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。然后，利用该符号来选择正和或负的正和归一化移位量。

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