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11. 发明授权

US08049319B2 Ultra wideband system-on-package 有权
标题翻译：超宽带系统级封装
公开(公告)号：US08049319B2
公开(公告)日：2011-11-01
申请号：US12604354
申请日：2009-10-22
申请人： In-Kwon Ju , In-Bok Yom , Ho-Jin Lee
发明人： In-Kwon Ju , In-Bok Yom , Ho-Jin Lee
IPC分类号： H01L23/02 , H01L23/053 , H01L23/12 , H01L23/34
CPC分类号： H01L23/66 , H01L23/552 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2224/48091 , H01L2224/73265 , H01L2924/1423 , H01L2924/19032 , H01L2924/19033 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.
摘要翻译：该研究公开了一种超宽带系统级封装（SoP）。 SoP包括一个包装体; 安装在封装主体上的第一集成电路; 连接到第一集成电路的第一信号传输单元; 连接到第一信号传输单元并包括板条线和槽线的信号通路; 以及连接到信号通道的第二信号传输单元。本研究的技术可以通过最小化在向外部电路传输信号的过程中发生的垂直转换期间出现的信号的不连续性来传输超宽带信号及其制造方法。

12. 发明授权

US07995578B2 Repetition apparatus and method for repeatedly transmitting and receiving data packet using different puncturing patterns 失效
标题翻译：用于使用不同的打孔模式重复地发送和接收数据分组的重复装置和方法
公开(公告)号：US07995578B2
公开(公告)日：2011-08-09
申请号：US12334043
申请日：2008-12-12
申请人： Pansoo Kim , In-Ki Lee , Dae-Ig Chang , Ho-Jin Lee , Namshik Kim , Bongseop Song , Hyuncheol Park
发明人： Pansoo Kim , In-Ki Lee , Dae-Ig Chang , Ho-Jin Lee , Namshik Kim , Bongseop Song , Hyuncheol Park
IPC分类号： H04J3/16
CPC分类号： H04L1/0071 , H04L1/0013 , H04L1/0068 , H04L1/08
摘要： Provided are repetition apparatus and method for repeatedly transmitting and receiving a data packet using different puncturing patterns to overcome signal attenuation and fading in a high speed mobile environment by repeatedly transmitting the duplicated information bit sequences with parity bits having a different puncturing pattern after channel-encoding the duplicated information bit. The repetition apparatus for repeatedly transmitting a data packet, includes a dual data generator for generating duplicated information bit sequences identical to each of information bit sequences to transmit, a channel encoder for dividing each of the duplicated information bit sequences into a plurality of information bits, and generating coded data packets alternately having a plurality of parity bits according to different puncturing patterns for each of the divided information bits, and a transmitter for transmitting the generated coded data packets sequentially.
摘要翻译：提供了一种重复装置和方法，用于使用不同的打孔模式重复地发送和接收数据包，以通过在频道编码之后重复地发送具有不同打孔图案的奇偶校验位的复制信息比特序列来克服高速移动环境中的信号衰减和衰落重复的信息位。用于重复发送数据分组的重复装置包括：双数据产生器，用于产生与要发送的每个信息比特序列相同的重复信息比特序列，用于将每个复制信息比特序列分成多个信息比特的信道编码器，以及根据用于每个分割的信息比特的不同的删截图案，交替地生成具有多个奇偶校验位的编码数据分组，以及发送器，用于顺序地发送所生成的编码数据分组。

13. 发明申请

US20110147946A1 WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME 失效
标题翻译： WAFER LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME
公开(公告)号：US20110147946A1
公开(公告)日：2011-06-23
申请号：US13027594
申请日：2011-02-15
申请人： In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
发明人： In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/11462 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/0106 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19043 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
摘要翻译：一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。在集成电路区域上形成第一金属层图案。通孔形成为延伸穿过第一金属层图案和集成电路区域。最终的金属层图案形成在第一金属层图案之上并且在通孔内。在通孔内形成插头。此后，形成钝化层以覆盖最终金属层图案。

14. 发明申请

US20110086486A1 Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein 有权
标题翻译：形成具有垂直扩展的基板通孔的集成电路芯片的方法
公开(公告)号：US20110086486A1
公开(公告)日：2011-04-14
申请号：US12969977
申请日：2010-12-16
申请人： Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
发明人： Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
IPC分类号： H01L21/768 , H01L21/02 , H01L21/28
CPC分类号： H01L23/528 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/06181 , H01L2224/13009 , H01L2224/16145 , H01L2224/16225 , H01L2224/48145 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311 , H01L2924/00012
摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。第一侧壁间隔层形成在互连孔的侧壁上。在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。然后用通孔电极填充互连孔和未切割凹部。去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

15. 发明申请

US20110053628A1 SERVICE PROVIDING SYSTEM AND METHOD IN SATELLITE COMMUNICATION SYSTEM 审中-公开
标题翻译：卫星通信系统中的服务提供系统和方法
公开(公告)号：US20110053628A1
公开(公告)日：2011-03-03
申请号：US12869186
申请日：2010-08-26
申请人： Hee-Wook Kim , Kunseok Kang , Do-Seob Ahn , Ho-Jin Lee
发明人： Hee-Wook Kim , Kunseok Kang , Do-Seob Ahn , Ho-Jin Lee
IPC分类号： H04B7/00
CPC分类号： H04B7/18539 , H04B7/2041
摘要： A service providing method in a satellite communication system includes: confirming positions of terminals when the terminals existing within a service area and intended to receive a service is connected to a satellite base station or a complementary terrestrial component; confirming first terminals, which communicate with the satellite base station, and second terminals, which communicate with the complementary terrestrial component, according to the positions of the terminals; allocating resources usable when communicating with the first terminals and resources usable when communicating with the second terminals; and providing a service to the terminals by using the allocated resources through multi-beams of the satellite base station and multi-beams of the complementary terrestrial component.
摘要翻译：卫星通信系统中的服务提供方法包括：当存在于业务区域内并且要接收业务的终端连接到卫星基站或互补地面组件时，确认终端的位置; 确定与卫星基站通信的第一终端，以及根据终端的位置与互补地面组件通信的第二终端; 分配与第一终端通信时可用的资源和与第二终端通信时可用的资源; 以及通过使用经由分配的资源通过卫星基站的多波束和互补地面分量的多波束向终端提供服务。

16. 发明申请

US20110031621A1 WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有应力消除间隔件的水平包装及其制造方法
公开(公告)号：US20110031621A1
公开(公告)日：2011-02-10
申请号：US12910260
申请日：2010-10-22
申请人： Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
发明人： Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
IPC分类号： H01L23/48 , H01L23/535
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/274 , H01L2225/06513 , H01L2225/06541 , H01L2924/01079 , H01L2924/01087
摘要： In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
摘要翻译：在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。金属手指通过应力消除间隔物与芯片的主体隔离。在一个示例中，这种隔离采取气隙的形式。在另一个实例中，这种隔离采用弹性体材料的形式。在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。

17. 发明申请

US20100285635A1 CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE 有权
标题翻译：芯片堆叠包装和制造芯片堆叠包装的方法
公开(公告)号：US20100285635A1
公开(公告)日：2010-11-11
申请号：US12840656
申请日：2010-07-21
申请人： Cha-Jea Jo , Myung-Kee Chung , Nam-Seog Kim , In-Young Lee , Seok-Ho Kim , Ho-Jin Lee , Ju-Il Choi , Chang-Woo Shin
发明人： Cha-Jea Jo , Myung-Kee Chung , Nam-Seog Kim , In-Young Lee , Seok-Ho Kim , Ho-Jin Lee , Ju-Il Choi , Chang-Woo Shin
IPC分类号： H01L21/60 , H01L21/50
CPC分类号： H01L23/3128 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/15311 , H01L2224/05599
摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.
摘要翻译：芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。基板具有形成在布线图案上的布线图案和种子层。每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。粘合层介于基片和芯片之一之间以及芯片之间。每个粘合层具有连接到第一通孔的第二通孔。插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

18. 发明授权

US07782823B2 Apparatus for allocating resources in DAMA satellite communication system and method thereof 失效
标题翻译：用于在DAMA卫星通信系统中分配资源的装置及其方法
公开(公告)号：US07782823B2
公开(公告)日：2010-08-24
申请号：US11305587
申请日：2005-12-16
申请人： Ki-Dong Lee , Deock-Gil Oh , Ho-Jin Lee
发明人： Ki-Dong Lee , Deock-Gil Oh , Ho-Jin Lee
IPC分类号： H04Q7/00
CPC分类号： H04L41/0896 , H04W28/20
摘要： Provided are an apparatus for estimating an increment in the number of packets arriving at a transmission queue of each terminal and allocating resources to terminals based on the increment in a Demand Assignment Multiple Access (DAMA) satellite communication system, and a method thereof. The method, includes the steps of: a) comparing a summation of requested time slot quantities of terminals with a total number of available time slots; and b) allocating the time slots as much as the requested time slot quantity to each terminal and allocating remaining time slots additionally in proportion to an estimated increase in the number of packets arriving at a transmission queue of each terminal. The apparatus can raise efficiency of resources allocation in DAMA communications and reduce the packet transmission time in a terminal transmission queue.
摘要翻译：提供了一种用于估计到达每个终端的传输队列的分组数量的增量的装置，并且基于在请求分配多路访问（DAMA）卫星通信系统中的增量向终端分配资源及其方法。该方法包括以下步骤：a）将所请求的终端时隙量的总和与可用时隙的总数进行比较; 以及b）将所请求的时隙数量的时隙分配给每个终端，并且分配剩余时隙，以与到达每个终端的传输队列的分组数量的估计增加成比例地分配剩余时隙。该装置可以提高DAMA通信中资源分配的效率，并减少终端传输队列中的分组传输时间。

19. 发明申请

US20090268841A1 POWER CONTROL SYSTEM AND METHOD FOR COMMUNICATION SYSTEM USING SPACE-TIME TRANSMIT DIVERSITY SCHEME 审中-公开
标题翻译：功率控制系统和使用空时传输多样性方案的通信系统的方法
公开(公告)号：US20090268841A1
公开(公告)日：2009-10-29
申请号：US12439329
申请日：2007-08-30
申请人： Byoung-Gi Kim , Kun-Seok Kang , Do-Seob Ahn , Ho-Jin Lee
发明人： Byoung-Gi Kim , Kun-Seok Kang , Do-Seob Ahn , Ho-Jin Lee
IPC分类号： H04B7/02 , H04L27/00 , H04L25/49
CPC分类号： H04B7/18543 , H04B7/0667 , H04B7/0891 , H04L1/0625 , H04W52/241
摘要： A power control system and method for communication system using space-time transmit diversity scheme. In the power control method, transmission power information of a plurality of antennas or a plurality of subcarriers is monitored. A new space-time code is generated by concatenating the monitored transmission power information and symbols to be transmitted. Symbols encoded using the generated space-time code are generated and the encoded symbols are transmitted. Accordingly, after determining the transmission power of each antenna, the transmission power information is monitored so that the transmission power information that does not experience the channel gain can be used at a next slot. Therefore, the performance degradation due to the round trip time can be reduced, thereby improving the system capacity and performance.
摘要翻译：一种使用时空发射分集方案的通信系统的功率控制系统和方法。在功率控制方法中，监视多个天线或多个子载波的发送功率信息。通过连接所监视的发送功率信息和要发送的符号来生成新的时空码。生成使用所生成的时空代码编码的符号，并且发送编码符号。因此，在确定每个天线的发送功率之后，监视发送功率信息，使得在下一个时隙可以使用不经历信道增益的发送功率信息。因此，可以降低由于往返时间引起的性能下降，从而提高系统容量和性能。

20. 发明申请

US20090261474A1 WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有应力消除间隔件的水平包装及其制造方法
公开(公告)号：US20090261474A1
公开(公告)日：2009-10-22
申请号：US12496176
申请日：2009-07-01
申请人： Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
发明人： Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
IPC分类号： H01L23/488 , H01L23/535
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/274 , H01L2225/06513 , H01L2225/06541 , H01L2924/01079 , H01L2924/01087
摘要： In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
摘要翻译：在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。金属手指通过应力消除间隔物与芯片的主体隔离。在一个示例中，这种隔离采取气隙的形式。在另一个实例中，这种隔离采用弹性体材料的形式。在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。

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