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    • 20. 发明授权
    • Method and system for configuring an array of logic devices
    • 用于配置逻辑器件阵列的方法和系统
    • US5946219A
    • 1999-08-31
    • US739606
    • 1996-10-30
    • Martin T. MasonScott C. EvansSandeep S. Aranake
    • Martin T. MasonScott C. EvansSandeep S. Aranake
    • H01L21/82G06F17/50
    • G06F17/5054
    • A system and method for partial reconfiguration of a gate array includes generating a netlist by placement and routing of a logic circuit. The netlist is accessed to modify logic cells configurations created by the place and route operation. Based on the modifications, a partial configuration bitstream containing only bitstrings which implement the modified logic cells is created. The partial configuration bitstream is downloaded to the gate array, thereby effectuating a partial reconfiguration of the gate array. In an alternate embodiment, a system in accordance with the present invention includes software utilities which allow an application program executing in a system containing a programmable gate array to reconfigure the array on-the-fly. The utilities include routines for modifying the design in response to external conditions detected during run-time. This approach obviates the need for providing a set of predetermined alternate designs, allowing the application to make that determination on its own.
    • 用于门阵列的部分重新配置的系统和方法包括通过逻辑电路的放置和布线生成网表。 访问网表以修改由位置和路由操作创建的逻辑单元配置。 基于修改,创建仅包含实现修改的逻辑单元的位串的部分配置比特流。 将部分配置比特流下载到门阵列,从而实现门阵列的部分重新配置。 在替代实施例中,根据本发明的系统包括允许在包含可编程门阵列的系统中执行的应用程序在运行中重新配置阵列的软件实用程序。 实用程序包括响应于在运行时检测到的外部条件修改设计的例程。 这种方法避免了提供一组预定的替代设计的需要,允许应用自己做出该确定。