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    • 13. 发明授权
    • Part arrangement optimizing method
    • 零件排列优化方法
    • US5600555A
    • 1997-02-04
    • US242888
    • 1994-05-16
    • Masanobu TakahashiKazuo Kyuma
    • Masanobu TakahashiKazuo Kyuma
    • G06F17/50G06F17/60
    • G06Q10/043
    • The part arrangement optimizing method of the present invention is a part arranging method capable of obtaining part arrangements having smaller evaluation function values rapidly, and the method improves block arrangements so that evaluation function values such as total route lengths become small as much as possible by replacing plural blocks or block sets to determine the arrangements of parts on the basis of the arrangements of the blocks. Furthermore, as aforementioned improving method of the blocks, such a method as assigns expected positional coordinate to each part and arranges a block to a block arranging position near to the expected positional coordinate while renewing the expected positional coordinate so as to be located at the position where the evaluation function value becomes smaller.
    • 本发明的部件排列优化方法是能够快速获得具有较小评估函数值的部件布置的部件排列方法,并且该方法改进了块布置,使得尽可能多的评估功能值(例如总路线长度)尽可能地变小 多个块或块组,以基于块的布置来确定部件的布置。 此外,作为块的上述改进方法,这种方法为每个部分分配期望的位置坐标,并且在更新预期位置坐标的同时将块布置在靠近预期位置坐标的块排列位置,以便位于该位置 其中评估函数值变小。
    • 14. 发明授权
    • Method of optimizing combination by neural network
    • 通过神经网络优化组合的方法
    • US5416889A
    • 1995-05-16
    • US308637
    • 1994-09-19
    • Masanobu TakahashiKazuo Kyuma
    • Masanobu TakahashiKazuo Kyuma
    • G06F15/18G06F17/50G06F19/00G06G7/60G06N3/00G06N3/04G06N3/08G06N99/00G06Q10/04G06F15/60
    • G06F17/5072G06N3/086
    • A neural network for solving the problem of the optimization of the arrangement of N (at least two) parts which are combined with each other through connecting wires. After the weights of the synapses of a neuron which is allotted to each part are initially set, a learning process is repeated a predetermined number of times while satisfying restricting conditions. In the learning process, the fittest neurons for all the coordinates of the positions at which the parts are disposed are selected in accordance with a predetermined standard while serially updating the weights of the synapses of the other neurons so as to satisfy the restricting conditions. After the fittest neurons for all the coordinates of the positions are selected, judgement is made as to whether or not the arrangement obtained in the current learning cycle is closer to an optimal arrangement than any other arrangement which has been obtained in previous learning cycles.
    • 一种用于解决通过连接线彼此组合的N(至少两个)部分的布置优化的问题的神经网络。 在分配给每个部分的神经元的突触的权重被初始设置之后,在满足限制条件的同时,学习过程重复预定次数。 在学习过程中,根据预定的标准选择适合于所有部位位置坐标的适合神经元,同时连续地更新神经元突触的重量,以满足限制条件。 在选择了用于所有位置坐标的适合神经元之后,判断当前学习周期中获得的排列是否比以前的学习周期中获得的任何其他布置更接近于最佳布置。
    • 16. 发明授权
    • Method of optimizing a combination using a neural network
    • 使用神经网络优化组合的方法
    • US5452400A
    • 1995-09-19
    • US212421
    • 1994-03-11
    • Masanobu TakahashiKazuo Kyuma
    • Masanobu TakahashiKazuo Kyuma
    • G06F17/50G06N3/08G06F15/18
    • G06F17/5072G06N3/086
    • A neural network for solving the problem of the optimization of the arrangement of at least two parts which are combined with each other through connecting wires. One neuron is assigned to each part. Each neuron has a synapse with a weight. Weights of the synapses of a neuron are initially set, and a learning process is repeated a while satisfying restricting conditions. In the learning process, the fittest neurons for all the coordinates of the positions at which the parts are disposed are selected in accordance with a predetermined standard while serially updating the weights of the synapses of the neurons so as to satisfy the restricting conditions. After the fittest neurons for all the coordinates of the positions are selected, judgment is made as to whether or not the arrangement obtained in the current learning cycle is closer to an optimal arrangement than any other arrangement which has been obtained in previous learning cycles. The optimal arrangement obtained from a set of learning cycles is provided as an indication of a quasi-optimal arrangement.
    • 一种用于解决通过连接线彼此组合的至少两个部分的布置优化的问题的神经网络。 每个部分分配一个神经元。 每个神经元都有一个重量的突触。 初始设置神经元突触的重量,并且在满足限制条件的同时重复学习过程。 在学习过程中,根据预定的标准选择适合于所有部位位置坐标的适合神经元,同时连续地更新神经元突触的重量,以满足限制条件。 在选择了用于所有位置坐标的适合神经元之后,判断当前学习周期中获得的排列是否比以前的学习周期中获得的任何其他布置更接近最佳布置。 提供从一组学习周期获得的最佳布置作为准最优布置的指示。
    • 17. 发明申请
    • Video display apparatus
    • 视频显示装置
    • US20080186413A1
    • 2008-08-07
    • US12003176
    • 2007-12-20
    • Jun SomeyaKazuo KyumaKazuhiko TsutsumiHiroaki SugiuraHironobu Yasui
    • Jun SomeyaKazuo KyumaKazuhiko TsutsumiHiroaki SugiuraHironobu Yasui
    • H04N5/66
    • H04N5/20H04N5/147H04N9/68
    • A video display apparatus generates luminance information for individual frames of a video signal from histograms of the luminance component of the video signal, and classifies the content of the video signal on the basis of this information. Color saturation information is also generated from color saturation histograms, and scene changes are detected. Video correction parameters and display control parameters are derived from the content classification and color saturation information. The video signal is corrected according to the video correction parameters, and displayed according to the display control parameters. Display characteristics suitable for the video content are thereby obtained. The parameters are changed when a scene change is detected, so that the viewer is not disturbed by the change in video display characteristics.
    • 视频显示装置从视频信号的亮度分量的直方图生成视频信号的各个帧的亮度信息,并根据该信息对视频信号的内容进行分类。 颜色饱和度信息也是从颜色饱和度直方图生成的,并且检测到场景变化。 视频校正参数和显示控制参数是从内容分类和色彩饱和度信息中得出的。 视频信号根据视频校正参数进行校正,并根据显示控制参数进行显示。 从而获得适合于视频内容的显示特性。 当检测到场景变化时,参数被改变,使得观看者不受视频显示特征的变化的干扰。
    • 20. 发明授权
    • Optical logic element with short switching time
    • 开关时间短的光逻辑元件
    • US4999688A
    • 1991-03-12
    • US475994
    • 1990-01-06
    • Kunihiko HaraKeisuke KojimaKazuo Kyuma
    • Kunihiko HaraKeisuke KojimaKazuo Kyuma
    • G02F3/02G06E3/00G11C7/00G11C11/42
    • G02F3/02G06E3/005G11C11/42G11C7/005Y10T307/773
    • An optical logic element includes an optical bistable npnp element for switching from a high resistance state to a low resistance state in response to electrical bias and incident light energy in which the switching time becomes shorter as the incident light energy becomes larger. The elements emit light in the low resistance on state. The optical logic element is designed for analog threshold processing of light energy. A plurality of optical bistable elements connected in parallel differentially threshold process incident light energy. An opto-electronic conversion apparatus includes linear arrays of light emitting elements, a two-dimensional array of optical memories, i.e., optical bistable elements, and linear light receiving element arrays arranged transverse to the light emitting element arrays, all integrated with each other. Corresponding light emitting elements, optical memories, and light receiving elements permit arbitrary transfers of signals. Periodic refresh light pulses maintain each optical memory in an established state.
    • 光学逻辑元件包括用于响应于入射光能量变大而使开关时间变短的电偏压和入射光能量从高电阻状态切换到低电阻状态的光学双稳态npnp元件。 元件在低电阻开状态下发光。 光逻辑元件设计用于光能的模拟阈值处理。 并联连接的多个光学双稳态元件,差分阈值处理入射光能量。 光电转换装置包括发光元件的线性阵列,光学存储器的二维阵列,即光学双稳态元件和横向于发光元件阵列布置的线性光接收元件阵列,它们彼此整合。 相应的发光元件,光存储器和光接收元件允许信号的任意传送。 周期性刷新光脉冲将每个光学存储器保持在建立状态。