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11. 发明申请

US20070109873A1 Non-volatile memory device having controlled bulk voltage and method of programming same 审中-公开
标题翻译：具有受控体积电压的非易失性存储器件及其编程方法
公开(公告)号：US20070109873A1
公开(公告)日：2007-05-17
申请号：US11649815
申请日：2007-01-05
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C7/10
CPC分类号： G11C16/30 , G11C16/10
摘要： Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.
摘要翻译：公开了一种非易失性存储器件及其编程方法。通过将字线电压，位线电压和体电压施加到器件内的存储器单元来编程非易失性存储器件。在器件的编程操作期间，体电压由第一泵产生。然而，在体电压超过预定检测电压的情况下，第二泵进一步被激活以便降低体电压。

12. 发明授权

US07149528B2 Method for controlling overload in digital mobile communication system 失效
标题翻译：数字移动通信系统过载控制方法
公开(公告)号：US07149528B2
公开(公告)日：2006-12-12
申请号：US09767563
申请日：2001-01-23
申请人： Young-Il Lim , Jae-Yong Jeong , Myoung-Ki Seol
发明人： Young-Il Lim , Jae-Yong Jeong , Myoung-Ki Seol
IPC分类号： H04Q7/20
CPC分类号： H04W24/08 , H04M3/365
摘要： A method for controlling an overload of a digital mobile communication system. The digital mobile communication system has a base transceiver station and a base station controller each of which has a database. The method for controlling the overload includes the steps of: a) initializing threshold values stored on the database as a predetermined value; b) monitoring each of utility rates of a control processor resource and a call resource; c) comparing the utility rates of the control processor resource and the call resource with the threshold values respectively, thereby obtaining overload grades of the control processor resource and the call resource; d) comparing the overload grade of the control processor resource with the overload grade of the call resource, thereby selecting one of the control processor resource and the call resource as a resource to be controlled, which has a higher overload grade; e) determining whether an overload occurs in the resource to be controlled; and f) if the overload occurs in the resource to be controlled, informing a base station manager of an occurrence in the resource to be controlled.
摘要翻译：一种用于控制数字移动通信系统的过载的方法。数字移动通信系统具有基站收发台和基站控制器，每个基站具有数据库。用于控制过载的方法包括以下步骤：a）将存储在数据库上的阈值初始化为预定值; b）监控控制处理器资源和呼叫资源的每个利用率; c）分别将控制处理器资源和呼叫资源的利用率与阈值进行比较，从而获得控制处理器资源和呼叫资源的过载等级; d）将控制处理器资源的过载等级与呼叫资源的过载等级进行比较，从而选择控制处理器资源和呼叫资源之一作为要控制的资源，具有较高的过载等级; e）确定在要控制的资源中是否发生过载; 以及f）如果在要控制的资源中发生过载，则向基站管理员通知要控制的资源中的发生。

13. 发明申请

US20060087888A1 Nonvolatile memory device and method of programming same 有权
标题翻译：非易失性存储器件及其编程方法
公开(公告)号：US20060087888A1
公开(公告)日：2006-04-27
申请号：US11106640
申请日：2005-04-15
申请人： Jae-Yong Jeong
发明人： Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/102
摘要： A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is typically interrupted or resumed in response to signals generated by a program controller and/or a detector monitoring the programming voltage.
摘要翻译：公开了一种非易失性存储器件及其编程方法。非易失性存储器件适于响应于提供给存储器单元的编程电压的变化而中断或恢复器件的存储器单元的编程操作。响应于由程序控制器和/或监视编程电压的检测器产生的信号，编程操作通常被中断或恢复。

14. 发明申请

US20060056237A1 Non-volatile memory device with scanning circuit and method 失效
标题翻译：具有扫描电路和方法的非易失性存储器件
公开(公告)号：US20060056237A1
公开(公告)日：2006-03-16
申请号：US11181163
申请日：2005-07-13
申请人： Jae-Yong Jeong
发明人： Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/32
摘要： I describe and claim an accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device comprises a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having a first value, and a programming unit to program the memory cells corresponding to the detected portions of the program data responsive to the scanning.
摘要翻译：我描述并要求加速位扫描非易失性存储器件和方法。非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，与程序数据相对应的每个存储器单元，用于检测具有第一值的程序数据的数据扫描单元，以及编程单元，用于对与检测到响应于扫描的节目数据的部分。

15. 发明授权

US08045376B2 Flash memory device with multi level cell and burst access method therein 失效
标题翻译：具有多级单元和突发存取方法的闪存器件
公开(公告)号：US08045376B2
公开(公告)日：2011-10-25
申请号：US12615374
申请日：2009-11-10
申请人： Jung-Woo Lee , Jae-Yong Jeong
发明人： Jung-Woo Lee , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C2211/5633
摘要： A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.
摘要翻译：一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字，重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

16. 发明授权

US07800944B2 Nonvolatile semiconductor memory device and programming method thereof 有权
标题翻译：非易失性半导体存储器件及其编程方法
公开(公告)号：US07800944B2
公开(公告)日：2010-09-21
申请号：US12129820
申请日：2008-05-30
申请人： Jin-Young Chun , Jae-Yong Jeong , Chi-Weon Yoon
发明人： Jin-Young Chun , Jae-Yong Jeong , Chi-Weon Yoon
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.
摘要翻译：公开了一种非易失性存储器件的非易失性存储器件和编程方法。非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作比第一编程操作的第一验证电压。

17. 发明授权

US07599219B2 Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals 有权
标题翻译：使用非均匀验证时间间隔支持增量式步进脉冲编程的闪存设备
公开(公告)号：US07599219B2
公开(公告)日：2009-10-06
申请号：US12031422
申请日：2008-02-14
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过用具有第一级高度（例如，DeltaV1）的编程电压的第一阶梯级序列驱动阵列中的选定字线，然后响应于验证，执行多个存储器编程操作（P）耦合到所选择的字线的存储单元中的至少一个是经过的存储单元，用具有低于第一台阶高度（例如，DeltaV2）的编程电压的第二阶梯顺序驱动所选择的字线。

18. 发明申请

US20090003075A1 FLASH MEMORY DEVICES AND PROGRAMMING METHODS THAT VARY PROGRAMMING CONDITIONS IN RESPONSE TO A SELECTED STEP INCREMENT 有权
标题翻译：闪存存储器件和编程方法，其中对于选择的阶段增量的响应的变化的编程条件
公开(公告)号：US20090003075A1
公开(公告)日：2009-01-01
申请号：US12134648
申请日：2008-06-06
申请人： In-Mo Kim , Jae-Yong Jeong , Chi-Weon Yoon
发明人： In-Mo Kim , Jae-Yong Jeong , Chi-Weon Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.
摘要翻译：一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

19. 发明申请

US20060291290A1 Circuit and Method for Adaptive Incremental Step-Pulse Programming in a Flash Memory Device 有权
标题翻译：闪存设备中自适应增量步进脉冲编程的电路和方法
公开(公告)号：US20060291290A1
公开(公告)日：2006-12-28
申请号：US11381140
申请日：2006-05-02
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有低于第一个字线的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线步高。

20. 发明授权

US07123528B2 Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof 有权
标题翻译：具有能够选择所有列选择晶体管的列预解码器的闪存器件及其压力测试方法
公开(公告)号：US07123528B2
公开(公告)日：2006-10-17
申请号：US10677841
申请日：2003-10-01
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C8/12 , G11C16/04 , G11C2029/1204 , G11C2029/2602
摘要： A column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.
摘要翻译：列预解码器包括用于输入所有列选择信号的缓冲单元，用于对缓冲单元和列地址的输出进行解码的解码器单元和用于响应于列选择晶体管的栅极耦合到列选择晶体管的列选择信号的电压电平的电平移位器解码器单元的输出。由于接地电压施加于位线，并且在应力测试期间对所有列选择信号施加高电压，所以可以缩短应力测试时间。

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