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11. 发明授权

US07880490B2 Wireless interface probe card for high speed one-shot wafer test and semiconductor testing apparatus having the same 有权
标题翻译：无线接口探针卡，用于高速单片晶圆测试和半导体测试装置
公开(公告)号：US07880490B2
公开(公告)日：2011-02-01
申请号：US12200716
申请日：2008-08-28
申请人： Sang-Hoon Lee , Kwang-Yong Lee , Se-Jang Oh , Young-Soo An
发明人： Sang-Hoon Lee , Kwang-Yong Lee , Se-Jang Oh , Young-Soo An
IPC分类号： G01R31/28
CPC分类号： G01R31/2889 , G01R31/3025
摘要： A wireless interface probe card includes a substrate member and a transmission member. The substrate member has a plurality of probe terminals arranged at a constant pitch. The probe terminals may directly contact a plurality of pads arranged at a constant pitch on each of a plurality of semiconductor chips arranged on a wafer to perform a test of the semiconductor chips arranged on the wafer. The transmission member is arranged on the substrate member, wirelessly receives a test signal and provides the received test signal to the pads of the wafer through the probe terminals, and wirelessly and externally transmits an electrical characteristic signal provided from the pads of the wafer through the probe terminals.
摘要翻译：无线接口探针卡包括基板部件和传输部件。基板构件具有以恒定间距排列的多个探针端子。探针端子可以直接接触布置在晶片上的多个半导体芯片中的每一个上以恒定间距布置的多个焊盘，以对布置在晶片上的半导体芯片进行测试。传输构件布置在基板构件上，无线地接收测试信号，并通过探针端子将接收到的测试信号提供给晶片的焊盘，并且通过以下方式无线地和外部地传输从晶片的焊盘提供的电特性信号探头端子。

12. 发明授权

US07538566B2 Electrical test system including coaxial cables 有权
标题翻译：电测试系统包括同轴电缆
公开(公告)号：US07538566B2
公开(公告)日：2009-05-26
申请号：US11926172
申请日：2007-10-29
申请人： Young-Soo An , Se-Jang Oh , Jung-Hyun Nam
发明人： Young-Soo An , Se-Jang Oh , Jung-Hyun Nam
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2889
摘要： An electrical test system includes a test head, a performance board, a probe card and coaxial cables. The performance board includes a first side and an opposite second side, where the first side of the performance board is electrically connected to the test head and the second side of the performance board includes first coaxial cable connection portions. The probe card includes a first side and an opposite second side, where the first side of the probe card includes second coaxial cable connection portions and the second side includes a wafer test probes. The coaxial cables respectively electrically connect the first coaxial cable connection portions of the performance board to the second coaxial cable connection portions of the probe card.
摘要翻译：电气测试系统包括测试头，演奏板，探针卡和同轴电缆。所述性能板包括第一侧和相对的第二侧，其中所述性能板的第一侧电连接到所述测试头，并且所述性能板的第二侧包括第一同轴电缆连接部分。探针卡包括第一侧和相对的第二侧，其中探针卡的第一侧包括第二同轴电缆连接部分，并且第二侧包括晶片测试探针。同轴电缆分别将性能板的第一同轴电缆连接部分电连接到探针卡的第二同轴电缆连接部分。

13. 发明授权

US06625766B1 Tester of semiconductor memory device and test method thereof 失效
标题翻译：半导体存储器件测试仪及其测试方法
公开(公告)号：US06625766B1
公开(公告)日：2003-09-23
申请号：US09512158
申请日：2000-02-24
申请人： Se-Jang Oh , Ki-Sang Kang
发明人： Se-Jang Oh , Ki-Sang Kang
IPC分类号： G11C2900
CPC分类号： G11C29/20 , G11C2029/0405
摘要： A test method of a tester of a semiconductor memory device which includes recording a test pattern into the semiconductor memory device, reading the recorded test pattern to compare with a expected pattern, detecting information on a defect of the semiconductor memory device with a result of the comparison and interpreting the information on the defect of the semiconductor memory device, the method comprising the steps of: setting up minimum and maximum values relevant to a desired capacity of the semiconductor memory device to be tested; counting up from the preset minimum to the preset maximum values; generating a carry signal by comparing the preset maximum value with the counted value when the counted value gets to the preset maximum value; and resetting a value to be counted if the carry signal is generated, to thereby generate addresses of the semiconductor memory device, and a tester of the semiconductor memory device comprising: minimum and maximum address registering means for saving minimum and maximum address values relevant to a desired capacity of the semiconductor memory device to be tested; address counting means for increasingly counting from the minimum value to generate addresses; and carry signal generating means for generating carry signals, if the addresses output from the address counting means and a signal output from the maximum address registering means are the same, to thereby reset the address counting means, so that a user of the tester does not have to make a new test program, providing convenience in performing a test and improving reliability in results of the test.
摘要翻译：一种半导体存储器件的测试器的测试方法，包括将测试图案记录到半导体存储器件中，读取记录的测试图案以与预期图案进行比较，检测关于半导体存储器件的缺陷的信息，结果是比较和解释关于半导体存储器件的缺陷的信息，该方法包括以下步骤：设置与要测试的半导体存储器件的期望容量相关的最小值和最大值; 从预设最小值到预设最大值; 当计数值达到预设最大值时，通过将预设最大值与计数值进行比较来产生进位信号; 并且如果产生进位信号，则重置要计数的值，从而生成半导体存储器件的地址，以及半导体存储器件的测试器，包括：最小和最大地址寄存装置，用于保存与a相关的最小和最大地址值要测试的半导体存储器件的期望容量; 地址计数装置，用于从最小值逐渐计数以产生地址; 以及用于产生进位信号的进位信号产生装置，如果从地址计数装置输出的地址和从最大地址登记装置输出的信号相同，从而复位地址计数装置，使得测试仪的用户不必须制定一个新的测试程序，提供方便的测试和提高测试结果的可靠性。

14. 发明授权

US06507801B1 Semiconductor device testing system 失效
标题翻译：半导体器件测试系统
公开(公告)号：US06507801B1
公开(公告)日：2003-01-14
申请号：US09697026
申请日：2000-10-25
申请人： Se-Jang Oh , Ki-Sang Kang , Jeong-Ho Bang
发明人： Se-Jang Oh , Ki-Sang Kang , Jeong-Ho Bang
IPC分类号： G06F300
CPC分类号： G01R31/31707 , G01R31/3183 , G01R31/318371
摘要： The present invention relates to a semiconductor device testing system having an advanced testing capability for performing tests on a semiconductor device. A system frame includes both normal and high-speed testing formatters, and a test head is arranged in electrical communication with the system frame. Normal PIN drivers are included to operate the testing system at a first frequency to transmit the signals required to perform tests at a normal speed. High-speed PIN drivers are also included to operate the testing system at a second frequency, higher than the first frequency, to transmit the signals required to perform tests at a higher speed. In this manner, the testing system of this invention is able-to achieve superior testing performance while reducing the overall system production cost.
摘要翻译：本发明涉及具有用于对半导体器件进行测试的先进测试能力的半导体器件测试系统。系统框架包括正常和高速测试格式化程序，测试头与系统框架电气通信。包括正常PIN驱动程序，以第一频率操作测试系统，以正常速度传输执行测试所需的信号。还包括高速PIN驱动程序，以高于第一个频率的第二个频率操作测试系统，以更高速度传输执行测试所需的信号。以这种方式，本发明的测试系统能够在降低整个系统生产成本的同时实现优异的测试性能。

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