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11. 发明授权

US07454586B2 Memory device commands 有权
标题翻译：内存设备命令
公开(公告)号：US07454586B2
公开(公告)日：2008-11-18
申请号：US11093705
申请日：2005-03-30
申请人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas D. Skelton , Bill H. Nale
发明人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas D. Skelton , Bill H. Nale
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C7/04 , G11C7/1045 , G11C11/4076
摘要： Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.
摘要翻译：关于物理参数和安全性的数据以及发送这样的数据的命令可以使用连接在两者之间的存储器总线在存储器件和存储器控制器之间传送。在一个实施例中，本发明包括在存储器总线上的存储器件处接收第一命令，第一命令不同于读取或写入命令，并且与第一命令一起接收第二命令，使用第一个命令未使用的行。

12. 发明申请

US20060133173A1 Method, apparatus, and system for active refresh management 有权
标题翻译：用于主动刷新管理的方法，装置和系统
公开(公告)号：US20060133173A1
公开(公告)日：2006-06-22
申请号：US11019881
申请日：2004-12-21
申请人： Sandeep Jain , Animesh Mishra , John Halbert
发明人： Sandeep Jain , Animesh Mishra , John Halbert
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40618 , G11C11/40622
摘要： A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.
摘要翻译：一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数，从而减少刷新期间消耗的功率量。

13. 发明申请

US20080056047A1 METHOD, APPARATUS, AND SYSTEM FOR ACTIVE REFRESH MANAGEMENT 有权
标题翻译：用于主动刷新管理的方法，装置和系统
公开(公告)号：US20080056047A1
公开(公告)日：2008-03-06
申请号：US11932470
申请日：2007-10-31
申请人： Sandeep Jain , Animesh Mishra , John Halbert
发明人： Sandeep Jain , Animesh Mishra , John Halbert
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40618 , G11C11/40622
摘要： A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.
摘要翻译：一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数，从而减少刷新期间消耗的功率量。

14. 发明授权

US07793037B2 Partial page scheme for memory technologies 有权
标题翻译：内存技术部分页面方案
公开(公告)号：US07793037B2
公开(公告)日：2010-09-07
申请号：US11140772
申请日：2005-05-31
申请人： Sandeep Jain , Animesh Mishra , Jim Kardach
发明人： Sandeep Jain , Animesh Mishra , Jim Kardach
IPC分类号： G06F12/00
CPC分类号： G11C7/1021 , G11C7/1045 , G11C8/12
摘要： Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.
摘要翻译：管理存储器的系统和方法提供用于检测激活被限制为部分页面大小的部分页面大小的存储器部分的请求，其中部分页面大小小于与存储器相关联的整个页面大小。在一个实施例中，检测请求可以包括识别与该请求相关联的行地址和部分页面地址，其中部分页面地址指示存储器部分被限制为部分页面大小。

15. 发明申请

US20060271748A1 Partial page scheme for memory technologies 有权
标题翻译：内存技术部分页面方案
公开(公告)号：US20060271748A1
公开(公告)日：2006-11-30
申请号：US11140772
申请日：2005-05-31
申请人： Sandeep Jain , Animesh Mishra , Jim Kardach
发明人： Sandeep Jain , Animesh Mishra , Jim Kardach
IPC分类号： G06F13/00
CPC分类号： G11C7/1021 , G11C7/1045 , G11C8/12
摘要： Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.
摘要翻译：管理存储器的系统和方法提供用于检测激活被限制为部分页面大小的部分页面大小的存储器部分的请求，其中部分页面大小小于与存储器相关联的整个页面大小。在一个实施例中，检测请求可以包括识别与该请求相关联的行地址和部分页面地址，其中部分页面地址指示存储器部分被限制为部分页面大小。

16. 发明申请

US20070005836A1 Memory having swizzled signal lines 审中-公开
标题翻译：存储器有信号线
公开(公告)号：US20070005836A1
公开(公告)日：2007-01-04
申请号：US11148160
申请日：2005-06-07
申请人： Sandeep Jain , George Vergis , John Halbert , Nilesh Shah
发明人： Sandeep Jain , George Vergis , John Halbert , Nilesh Shah
IPC分类号： G06F13/38
CPC分类号： G06F13/4013 , G11C5/06 , G11C7/04 , G11C7/1006 , G11C8/20
摘要： Swizzle information for signal lines on a memory component may be stored on the memory component. The swizzle information may be transmitted to a memory controller which may include logic to receive the swizzle information which is then used to deswizzle data received from the memory component. Data may be transmitted from a memory device to a memory controller in a format that is tolerant of swizzling on signal lines between the device and the controller. The format may include codes having unique of numbers of values. Data may be sent in multi-code bursts that divide a data range into progressively smaller ranges. Other embodiments are described and claimed.
摘要翻译：存储器组件上的信号线的交换信息可以存储在存储器组件上。交换信息可以被发送到存储器控制器，存储器控制器可以包括用于接收转移信息的逻辑，然后用于去除从存储器组件接收的数据。数据可以以容许在设备和控制器之间的信号线上进行转换的格式从存储器件发送到存储器控制器。该格式可以包括具有唯一值的值的代码。可以以将多个数字范围分割成逐渐变小的多码脉冲串来发送数据。描述和要求保护其他实施例。

17. 发明授权

US10836765B2 Process for the preparation of valacyclovir 有权
公开(公告)号：US10836765B2
公开(公告)日：2020-11-17
申请号：US16081944
申请日：2017-02-24
申请人： AUROBINDO PHARMA LTD , Sandeep Jain , Komel Ansari , Subramanyam Maddala , Sivakumaran Meenakshisundaram
发明人： Sandeep Jain , Komel Ansari , Subramanyam Maddala , Sivakumaran Meenakshisundaram
IPC分类号： C07D473/18 , B01J19/00
CPC分类号： C07D473/18 , B01J19/0093 , B01J2219/00033
摘要： The present invention relates to an improved process for the preparation of Valacyclovir or pharmaceutically acceptable salts thereof, which comprises reaction of amine-protected Valacyclovir or its salt with deprotecting agent in a continuous flow reactor.

18. 发明授权

US10505871B1 Future messaging maximizing contextual relevancy and minimizing information overload based distractions 有权
公开(公告)号：US10505871B1
公开(公告)日：2019-12-10
申请号：US15827172
申请日：2017-11-30
申请人： Sandeep Jain
发明人： Sandeep Jain
IPC分类号： H04L12/58
CPC分类号： H04L51/04 , H04L51/12 , H04L51/24 , H04L51/28
摘要： A messaging server with a future message storage space for future messages, each being a sender created message not yet delivered to a recipient that has an associated sender specified message delivery time. Recipient specific delivery block details are specified for a set of delivery blocks for future messages. The future messages are received processed and stored. Until the respective sender specified message delivery time a respective one of the set of senders is able to retract and edit a corresponding one of the future messages. Future messages are delivered at the delivery time consistent with the delivery blocks. After delivery the sender is unable to retract and edit a corresponding delivered message. Future messages do not alert a recipient of arrival until the sender established delivery time, which minimizes cognitive distractions and provides the sender with notice for anticipating a time of response, without overly distracting the recipient.

19. 发明授权

US09229890B2 Method and a system for integrating data from a source to a destination 有权
标题翻译：方法和用于将数据从源到目标集成的系统
公开(公告)号：US09229890B2
公开(公告)日：2016-01-05
申请号：US13457497
申请日：2012-04-27
申请人： Sandeep Jain , Prakash Chandra Tiwary
发明人： Sandeep Jain , Prakash Chandra Tiwary
IPC分类号： G06F17/30 , G06F13/22
CPC分类号： G06F13/22 , G06F11/2082 , G06F17/30008 , G06F17/30575
摘要： The embodiments herein provide a system and a method for integrating a data from a source to a destination. The method comprises generating a global-id, setting an event-id corresponding to an entity id in the global id, polling a data from a source, sorting changes of a source system based on a time of update and an entity id, creating and comparing an old as of state value and a new as of state value for each field for each update in the entity in the source and destination to detect a conflict on an entity, sending a time of update in the entity and a revision id of a change to the destination, comparing the global id with an event id for each entity at the destination to detect a presence of an entity in the destination and processing an entity at the destination based an event id.
摘要翻译：这里的实施例提供了用于将来自源到目的地的数据进行集成的系统和方法。该方法包括生成global-id，设置与全局id中的实体id相对应的事件id，轮询来自源的数据，根据更新时间和实体id对源系统的改变进行排序，创建和将来自源和目的地中的实体中的每个更新的每个字段的状态值和状态值的新的状态值进行比较以检测实体上的冲突，在实体中发送更新时间和修改ID 将目的地的每个实体的全局id与事件ID进行比较，以检测目的地中的实体的存在并根据事件ID处理目的地的实体。

20. 发明授权

US09053035B1 Multi-threaded system for performing atomic binary translations 有权
标题翻译：用于执行原子二进制翻译的多线程系统
公开(公告)号：US09053035B1
公开(公告)日：2015-06-09
申请号：US14088446
申请日：2013-11-25
申请人： Ashish Mathur , Sandeep Jain
发明人： Ashish Mathur , Sandeep Jain
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F9/3004 , G06F8/45 , G06F8/52 , G06F9/45558
摘要： A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.
摘要翻译：多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本链接指令与存储在存储条件共享存储器地址中的数据相同。

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