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11. 发明授权

US08914618B2 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource 有权
标题翻译：与异构资源的指令集基于架构的间隔器通信
公开(公告)号：US08914618B2
公开(公告)日：2014-12-16
申请号：US11321779
申请日：2005-12-29
申请人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
发明人： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
IPC分类号： G06F9/30 , G06F15/76 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。可以使用接口来提供这些资源之间的通信。通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。此外，指令定序器和加速器可以并行地执行操作。描述和要求保护其他实施例。

12. 发明申请

US20070150900A1 Data structure and management techniques for local user-level thread data 有权
标题翻译：本地用户级线程数据的数据结构和管理技术
公开(公告)号：US20070150900A1
公开(公告)日：2007-06-28
申请号：US11321763
申请日：2005-12-27
申请人： Richard Hankins , Gautham Chinya , Hong Wang , David Poulsen , Shirish Aundhe , John Shen , Sanjiv Shah , Baiju Patel
发明人： Richard Hankins , Gautham Chinya , Hong Wang , David Poulsen , Shirish Aundhe , John Shen , Sanjiv Shah , Baiju Patel
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： Data structure creation, organization and management techniques for data local to user-level threads are provided. Other embodiments are also described and claimed.
摘要翻译：提供数据结构创建，用户级线程本地数据的组织和管理技术。还描述和要求保护其他实施例。

13. 发明授权

US07610448B2 Obscuring memory access patterns 有权
标题翻译：模糊内存访问模式
公开(公告)号：US07610448B2
公开(公告)日：2009-10-27
申请号：US11646642
申请日：2006-12-27
申请人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
发明人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/14 , G06F11/00 , G06F12/16 , G06F15/18 , G08B23/00
CPC分类号： G06F12/0842 , G06F9/30047 , G06F12/1458 , G06F21/52 , G06F21/78
摘要： For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
摘要翻译：对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

14. 发明申请

US20100299479A1 OBSCURING MEMORY ACCESS PATTERNS 有权
标题翻译：记忆存取模式
公开(公告)号：US20100299479A1
公开(公告)日：2010-11-25
申请号：US12562041
申请日：2009-09-17
申请人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
发明人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/30047 , G06F12/1458 , G06F21/52 , G06F21/78
摘要： For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
摘要翻译：对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

15. 发明授权

US08078801B2 Obscuring memory access patterns 有权
标题翻译：模糊内存访问模式
公开(公告)号：US08078801B2
公开(公告)日：2011-12-13
申请号：US12562041
申请日：2009-09-17
申请人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
发明人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
IPC分类号： G06F12/12 , G06F11/30
CPC分类号： G06F12/0842 , G06F9/30047 , G06F12/1458 , G06F21/52 , G06F21/78
摘要： For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
摘要翻译：对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

16. 发明申请

US20080162816A1 Obscuring memory access patterns 有权
标题翻译：模糊内存访问模式
公开(公告)号：US20080162816A1
公开(公告)日：2008-07-03
申请号：US11646642
申请日：2006-12-27
申请人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
发明人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/30047 , G06F12/1458 , G06F21/52 , G06F21/78
摘要： For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
摘要翻译：对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

17. 发明申请

US20190130104A1 SIDE-CHANNEL EXPLOIT DETECTION 审中-公开
公开(公告)号：US20190130104A1
公开(公告)日：2019-05-02
申请号：US16233810
申请日：2018-12-27
申请人： Paul Carlson , Rahuldeva Ghosh , Baiju Patel , Zhong Chen
发明人： Paul Carlson , Rahuldeva Ghosh , Baiju Patel , Zhong Chen
IPC分类号： G06F21/56 , G06F12/0802 , G06N20/00 , G06F3/06 , G06F21/62
摘要： The present disclosure is directed to systems and methods for detecting side-channel exploit attacks such as Spectre and Meltdown. Performance monitoring circuitry includes first counter circuitry to monitor CPU cache misses and second counter circuitry to monitor DTLB load misses. Upon detecting an excessive number of cache misses and/or load misses, the performance monitoring circuitry transfers the first and second counter circuitry data to control circuitry. The control circuitry determines a CPU cache miss to DTLB load miss ratio for each of a plurality of temporal intervals. The control circuitry the identifies, determines, and/or detects a pattern or trend in the CPU cache miss to DTLB load miss ratio. Upon detecting a deviation from the identified CPU cache miss to DTLB load miss ratio pattern or trend indicative of a potential side-channel exploit attack, the control circuitry generates an output to alert a system user or system administrator.

18. 发明授权

US06915431B1 System and method for providing security mechanisms for securing network communication 有权
标题翻译：提供用于保护网络通信的安全机制的系统和方法
公开(公告)号：US06915431B1
公开(公告)日：2005-07-05
申请号：US09472314
申请日：1999-12-22
申请人： Anil Vasudevan , Baiju Patel , Marc Jalfon
发明人： Anil Vasudevan , Baiju Patel , Marc Jalfon
IPC分类号： G06F11/30 , G06F15/16 , G06F15/173 , G06F15/177 , H04L9/00 , H04L29/06
CPC分类号： H04L63/0428 , H04L63/06
摘要： A system and method of providing security mechanisms for securing traffic communicated from a server system to a client system independent of the state of the client system. The server system determines whether the client system has entered an operational state. When the client system is operational, key exchange processes are initiated between the two systems, the results of the key exchange processes being the parameters for use in securing traffic communication between the two systems. The results are stored in the client system. The results are inhibited from being updated in the client system until the server system is successful in completely executing another set of key exchange processes. The results are updated with the results obtained from successful execution of the other set of key exchange processes if the execution of the other set is successful. The traffic communication is thus secured based on whatever results are stored in the client system.
摘要翻译：一种提供安全机制的系统和方法，用于保护从服务器系统传递到客户机系统的流量，而与客户端系统的状态无关。服务器系统确定客户端系统是否已进入运行状态。当客户端系统运行时，在两个系统之间启动密钥交换过程，密钥交换过程的结果是用于保护两个系统之间的流量通信的参数。结果存储在客户端系统中。在客户端系统中禁止结果被更新，直到服务器系统成功完成另一组密钥交换过程。如果另一组的执行成功，结果将更新成功执行另一组密钥交换过程的结果。因此，基于客户端系统中存储的任何结果来确保流量通信。

19. 发明申请

US20170017791A1 RETURN ADDRESS OVERFLOW BUFFER 有权
标题翻译：返回地址溢出缓冲区
公开(公告)号：US20170017791A1
公开(公告)日：2017-01-19
申请号：US14798134
申请日：2015-07-13
申请人： Jason W. Brandt , Vedvyas Shanbhogue , Baiju Patel
发明人： Jason W. Brandt , Vedvyas Shanbhogue , Baiju Patel
IPC分类号： G06F21/56
CPC分类号： G06F21/52
摘要： Embodiments of an invention for a return address overflow buffer are disclosed. In one embodiment, a processor includes a stack pointer to store a reference to a first return address stored on a stack, an obscured address stack pointer to store a reference to an encrypted second return address stored in a memory, hardware to decrypt the encrypted second return address to generate a decrypted second return address, and a return address verification logic, responsive to receiving a return instruction, to compare the first return address to the decrypted second return address.
摘要翻译：公开了一种用于返回地址溢出缓冲器的发明的实施例。在一个实施例中，处理器包括堆栈指针，用于存储对存储在堆栈上的第一返回地址的引用，模糊地址堆栈指针，用于存储对存储在存储器中的加密的第二返回地址的引用，硬件来解密加密的第二返回地址以产生解密的第二返回地址，以及返回地址验证逻辑，响应于接收到返回指令，将第一返回地址与解密的第二返回地址进行比较。

20. 发明申请

US20160092702A1 CRYPTOGRAPHIC PONTER ADDRESS ENCODING 有权
标题翻译： CRYPTOGRAPHIC PONTER地址编码
公开(公告)号：US20160092702A1
公开(公告)日：2016-03-31
申请号：US14498540
申请日：2014-09-26
申请人： David M. Durham , Baiju Patel
发明人： David M. Durham , Baiju Patel
IPC分类号： G06F21/72 , G06F21/55
CPC分类号： G06F12/1408 , G06F21/556 , G06F21/72 , G06F2212/1052 , G06F2221/034 , G06F2221/2107 , H04L63/0435 , H04L63/061 , H04L63/1433
摘要： A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.
摘要翻译：计算设备包括用于保护由处理器用于执行存储器访问（例如，读/写/执行）操作的间接地址（例如，指针）的技术。计算设备使用元数据和加密算法对间接地址进行编码。元数据可以存储在间接地址的未使用部分中。

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