专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US09142768B2 Resistive memory with small electrode and method for fabricating the same 有权
标题翻译：具有小电极的电阻记忆及其制造方法
公开(公告)号：US09142768B2
公开(公告)日：2015-09-22
申请号：US13698799
申请日：2012-05-02
申请人： Yimao Cai , Jun Mao , Ru Huang , Shenghu Tan , Yinglong Huang , Yue Pan
发明人： Yimao Cai , Jun Mao , Ru Huang , Shenghu Tan , Yinglong Huang , Yue Pan
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.
摘要翻译：公开了涉及具有与ULSI中的半导体电阻性存储器的领域相关的具有小电极的电阻性存储器的系统和方法。示例性电阻存储器可以依次包括Al电极层，SiO 2层，Si层，电阻材料层和下电极层，其中Al电极层和电阻材料层通过一个或多个导电沟道电连接并且通过SiO 2层中的缺陷将Al材料穿过Si层而将Si材料溶解到Al材料中而形成导电通道。方法可以包括在衬底上形成下电极层，电阻层，Si层和SiO 2层; 在SiO 2层上制造Al电极层; 对所得到的结构进行退火处理。与本文的创新一致，可以通过常规方法获得小电极。

12. 发明申请

US20120099381A1 EMBEDDED NON-VOLATILE MEMORY CELL, OPERATION METHOD AND MEMORY ARRAY THEREOF 审中-公开
标题翻译：嵌入式非易失性存储器单元，其操作方法和存储器阵列
公开(公告)号：US20120099381A1
公开(公告)日：2012-04-26
申请号：US13380414
申请日：2011-05-19
申请人： Yimao Cai , Poren Tang , Ru Huang , Xiaoyan Xu
发明人： Yimao Cai , Poren Tang , Ru Huang , Xiaoyan Xu
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/0433 , H01L27/11526
摘要： The present invention discloses an embedded non-volatile memory cell, an operation method and a memory array thereof. The method includes using a gate of a selection transistor as a floating gate of a memory, and using a source electrode and a drain electrode of the selection transistor as a source electrode and a drain electrode of the memory; and then changing a threshold of the device by varying the electrode voltages, thereby realizing a storage and change of information. The invention has advantages of a small area, a low operating voltage, high operating speed and high reliability.
摘要翻译：本发明公开了一种嵌入式非易失性存储单元，其操作方法及其存储器阵列。该方法包括使用选择晶体管的栅极作为存储器的浮置栅极，并且使用选择晶体管的源电极和漏电极作为存储器的源电极和漏电极; 然后通过改变电极电压来改变器件的阈值，从而实现信息的存储和改变。本发明具有面积小，工作电压低，工作速度快，可靠性高等优点。

13. 发明授权

US08593848B2 Programming method for programming flash memory array structure 有权
标题翻译： Flash存储阵列结构编程方法
公开(公告)号：US08593848B2
公开(公告)日：2013-11-26
申请号：US13146005
申请日：2011-04-21
申请人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
发明人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
IPC分类号： G11C5/06
CPC分类号： G11C16/10 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.
摘要翻译：本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

14. 发明申请

US20120243313A1 SEMICONDUCTOR MEMORY ARRAY AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：半导体存储器阵列及其编程方法
公开(公告)号：US20120243313A1
公开(公告)日：2012-09-27
申请号：US13146005
申请日：2011-04-21
申请人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
发明人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.
摘要翻译：本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

15. 发明授权

US08513639B2 Resistive-switching memory and fabrication method thereof 有权
标题翻译：电阻式开关存储器及其制造方法
公开(公告)号：US08513639B2
公开(公告)日：2013-08-20
申请号：US13254570
申请日：2011-04-12
申请人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
发明人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.
摘要翻译：本发明公开了一种电阻式开关存储器及其制造方法。电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部电极为板状。底部电极的峰值结构降低了器件的功耗。其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。整个制造工艺简单，可以实现高集成度的装置。

16. 发明授权

US08536639B2 I-shape floating gate for flash memory device and fabricating the same 有权
标题翻译：用于闪存器件的I形浮动栅极和制造它们
公开(公告)号：US08536639B2
公开(公告)日：2013-09-17
申请号：US13498585
申请日：2011-11-30
申请人： Yimao Cai , Song Mei , Ru Huang
发明人： Yimao Cai , Song Mei , Ru Huang
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273
摘要： The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.
摘要翻译：本发明公开了一种闪存器件的浮动栅极结构及其制造方法，涉及超大规模集成电路的制造技术中的非易失性存储器。在本发明中，通过在闪速存储器的标准处理中，即通过添加三个步骤的沉积，两个步骤的蚀刻和CMP的一个步骤来修改浮动栅极的制造，形成一个形状的浮动栅极。除了这些步骤之外，所有其他步骤与闪存过程的标准过程相同。通过本发明，可以有效地改善耦合比，并且可以降低相邻器件之间的串扰，而不增加额外的光掩模，并且几乎不增加工艺复杂性，这对于提高编程速度和可靠性非常重要。

17. 发明授权

US08995165B2 Resistive memory cell 有权
标题翻译：电阻记忆单元
公开(公告)号：US08995165B2
公开(公告)日：2015-03-31
申请号：US13522858
申请日：2012-02-22
申请人： Yimao Cai , Zhenni Wan , Ru Huang
发明人： Yimao Cai , Zhenni Wan , Ru Huang
IPC分类号： G11C11/00 , H01L45/00 , H01L27/24 , G11C13/00
CPC分类号： H01L45/12 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array.
摘要翻译：本发明公开了一种电阻式存储单元，其包括单极型RRAM和作为串联连接到单极型RRAM的选择晶体管的MOS晶体管，其中MOS晶体管制造在部分耗尽SOI衬底上，并为程序提供大电流，通过使用SOI衬底的固有浮动效应擦除RRAM。本发明利用SOI器件的浮动效应，其中在相同的宽度/长度比下，SOI衬底上的MOS晶体管可以比在体硅上提供比MOS晶体管更大的源极/漏极电流，使得占据的面积由选择晶体管减少，这有利于RRAM阵列的集成。

18. 发明申请

US20140268988A1 RESISTIVE MEMORY CELL 有权
标题翻译：电阻记忆体
公开(公告)号：US20140268988A1
公开(公告)日：2014-09-18
申请号：US13522858
申请日：2012-02-22
申请人： Yimao Cai , Zhenni Wan , Ru Huang
发明人： Yimao Cai , Zhenni Wan , Ru Huang
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/12 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array.
摘要翻译：本发明公开了一种电阻式存储单元，其包括单极型RRAM和作为串联连接到单极型RRAM的选择晶体管的MOS晶体管，其中MOS晶体管制造在部分耗尽SOI衬底上，并为程序提供大电流，通过使用SOI衬底的固有浮动效应擦除RRAM。本发明利用SOI器件的浮动效应，其中在相同的宽度/长度比下，SOI衬底上的MOS晶体管可以比在体硅上提供比MOS晶体管更大的源极/漏极电流，使得占据的面积由选择晶体管减少，这有利于RRAM阵列的集成。

19. 发明申请

US20140017870A1 Method for Inhibiting Programming Disturbance of Flash Memory 审中-公开
标题翻译：禁止闪存编程故障的方法
公开(公告)号：US20140017870A1
公开(公告)日：2014-01-16
申请号：US13510618
申请日：2011-10-28
申请人： Yimao Cai , Ru Huang
发明人： Yimao Cai , Ru Huang
IPC分类号： H01L21/265
CPC分类号： H01L21/26586 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： Disclosed herein is a method for inhibiting a programming disturbance of a flash memory, which relates to a technical field of a non-volatile memory in ultra-large-scale integrated circuit fabrication technologies. In the present invention, an dopant gradient of a PN junction between a substrate and a drain is reduced by adding a step of performing an angled ion implantation of donor dopants into a standard process for a flash memory, so that an electric field of the PN junction between the substrate and the drain is reduced, and consequently the programming disturbance is inhibited. Meanwhile, a dopant gradient of the PN junction between a channel and the drain is maintained, so that an electric field of the PN junction between the channel and the drain, which is necessary for programming, is maintained, and thus the programming efficiency and the programming speed can be ensured. The programming disturbance can be effectively inhibited without increasing numbers of masks used for photolithography according to the invention, thus the present invention is significantly advantageous to the improvement of the flash memory reliability.
摘要翻译：本文公开了一种用于抑制闪存的编程干扰的方法，其涉及超大规模集成电路制造技术中的非易失性存储器的技术领域。在本发明中，通过添加将供体掺杂剂成角度离子注入到闪速存储器的标准工艺中的步骤来减小衬底和漏极之间的PN结的掺杂剂梯度，使得PN的电场衬底和漏极之间的接合被减小，因此编程干扰被抑制。同时，保持沟道和漏极之间的PN结的掺杂剂梯度，从而保持编程所需的沟道和漏极之间的PN结的电场，从而编程效率和可以确保编程速度。在不增加根据本发明的用于光刻的掩模数量的情况下，可以有效地抑制编程干扰，因此本发明对于提高闪速存储器可靠性是显着有利的。

20. 发明申请

US20130099300A1 Floating Gate Structure of Flash Memory Device and Method for Fabricating the Same 有权
标题翻译：闪存设备的浮动门结构及其制造方法
公开(公告)号：US20130099300A1
公开(公告)日：2013-04-25
申请号：US13498585
申请日：2011-11-30
申请人： Yimao Cai , Song Mei , Ru Huang
发明人： Yimao Cai , Song Mei , Ru Huang
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L21/28273
摘要： The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.
摘要翻译：本发明公开了一种闪存器件的浮动栅极结构及其制造方法，涉及超大规模集成电路的制造技术中的非易失性存储器。在本发明中，通过在闪速存储器的标准处理中，即通过添加三个步骤的沉积，两个步骤的蚀刻和CMP的一个步骤来修改浮动栅极的制造，形成I形的浮动栅极。除了这些步骤之外，所有其他步骤与闪存过程的标准过程相同。通过本发明，可以有效地改善耦合比，并且可以降低相邻器件之间的串扰，而不增加额外的光掩模，并且几乎不增加工艺复杂性，这对于提高编程速度和可靠性非常重要。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式