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11. 发明授权

US08605847B2 Receiver training with cycle slip detection and correction 有权
标题翻译：接收机训练与周期滑移检测和校正
公开(公告)号：US08605847B2
公开(公告)日：2013-12-10
申请号：US13043908
申请日：2011-03-09
申请人： Mohammad Mobin , Mark Trafford , Ye Liu , Vladimir Sindalovsky , Amaresh Malipatil
发明人： Mohammad Mobin , Mark Trafford , Ye Liu , Vladimir Sindalovsky , Amaresh Malipatil
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04L7/0083 , H04L2025/037
摘要： In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.
摘要翻译：在所描述的实施例中，收发器包括具有眼睛监视器和周期滑移监视器的时钟和数据恢复模块（CDR）。循环滑移检测器监测CDR锁定状态，其可以通过在采样和/或转换定时检测中检测到滑移。循环滑移检测器提供检查点以感测系统发散，允许恢复CDR锁的机制。另外，当CDR超出锁定时，自适应设置的各种参数（例如，均衡器参数）在系统发散期间可能是无效的。因此，这些参数可能被系统声明为无效，未被使用。

12. 发明申请

US20090175395A1 DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO 有权
标题翻译：具有可编程内容描述信息的仲裁输入的数据对齐方法
公开(公告)号：US20090175395A1
公开(公告)日：2009-07-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

13. 发明授权

US07995695B2 Data alignment method for arbitrary input with programmable content deskewing info 有权
标题翻译：用于可编程内容的任意输入的数据对齐方法
公开(公告)号：US07995695B2
公开(公告)日：2011-08-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser Ahmed , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser Ahmed , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

14. 发明申请

US20060273941A1 Content deskewing for multichannel synchronization 有权
公开(公告)号：US20060273941A1
公开(公告)日：2006-12-07
申请号：US11143370
申请日：2005-06-02
申请人： Ravikumar Charath , Vladimir Sindalovsky , Lane Smith
发明人： Ravikumar Charath , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H04J3/0632 , H04J3/0685
摘要： The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal. The data alignment signal is then read in all channels during the next read cycle, followed by subsequent reading of deskewed or otherwise synchronized data, such as for conversion of parallel data into serial data for subsequent data transmission.

15. 发明申请

US20120257693A1 CDR WITH SIGMA-DELTA NOISE-SHAPED CONTROL 有权
标题翻译： CDR与SIGMA-DELTA噪声控制
公开(公告)号：US20120257693A1
公开(公告)日：2012-10-11
申请号：US13081941
申请日：2011-04-07
申请人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
发明人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
IPC分类号： H04L27/06
CPC分类号： H04L7/033 , H03L7/101 , H04L7/0004 , H04L25/03057
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
摘要翻译：在所描述的实施例中，接收机包括具有VCO的积分环路控制中的压控振荡器（VCO）和Σ-Δ调制器的时钟和数据恢复（CDR）模块。当与积分环路中没有Σ-Δ调制器的环路相比时，通过Sigma-Delta调制器提供更精细的分辨率降低了积分控制环路中的量化噪声。在基于VCO的CDR的积分环路控制中的Σ-Δ调制降低了VCO积分字控制的有效量化，允许比例环路控制补偿以减少VCO积分字控制的有效量化，以及ii）增强接收器抖动存在频率偏离标称速率的串行数据的周期抖动的容限以及标称频率由扩频时钟调制的串行数据。

16. 发明申请

US20060268958A1 Methods and apparatus for spread spectrum generation using a voltage controlled delay loop 有权
标题翻译：使用电压控制延迟环路进行扩频生成的方法和装置
公开(公告)号：US20060268958A1
公开(公告)日：2006-11-30
申请号：US11141695
申请日：2005-05-31
申请人： Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H04B1/00
CPC分类号： H04B15/02 , H04B2215/067
摘要： Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
摘要翻译：提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。公开了一种扩频发生器电路，其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器，用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号，其中所述输出在所述至少两个信号的相位之间变化生成扩频。使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱，并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。

17. 发明申请

US20060267635A1 Multiple phase detection for delay loops 有权
标题翻译：延迟环路的多相检测
公开(公告)号：US20060267635A1
公开(公告)日：2006-11-30
申请号：US11138703
申请日：2005-05-26
申请人： Peter Metz , Vladimir Sindalovsky , Lane Smith
发明人： Peter Metz , Vladimir Sindalovsky , Lane Smith
IPC分类号： G01R29/00
CPC分类号： H03L7/07 , H03L7/087 , H03L7/097 , H03L7/0998 , H04L7/033
摘要： A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.
摘要翻译：电路（例如，接收器）具有延迟环路（例如，电压控制的延迟环路）和至少两个相位检测器（PD），其中每个PD比较由延迟环路产生的不同的时钟信号对。然后使用不同PD的输出来产生用于调整由延迟环路中的延迟元件提供的延迟的控制信号。在一个实现中，控制信号指示仅当两个PD同意该调整时才应进行延迟调整。这种多PD技术可以减少由延迟环使用的参考时钟信号中的非50％占空比产生其多个时钟信号的抖动。

18. 发明授权

US08494092B2 CDR with sigma-delta noise-shaped control 有权
标题翻译： CDR具有Σ-Δ噪声形控制
公开(公告)号：US08494092B2
公开(公告)日：2013-07-23
申请号：US13081941
申请日：2011-04-07
申请人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
发明人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H03L7/101 , H04L7/0004 , H04L25/03057
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
摘要翻译：在所描述的实施例中，接收机包括具有VCO的积分环路控制中的压控振荡器（VCO）和Σ-Δ调制器的时钟和数据恢复（CDR）模块。当与积分环路中没有Σ-Δ调制器的环路相比时，通过Sigma-Delta调制器提供更精细的分辨率降低了积分控制环路中的量化噪声。在基于VCO的CDR的积分环路控制中的Σ-Δ调制降低了VCO积分字控制的有效量化，允许比例环路控制补偿以减少VCO积分字控制的有效量化，以及ii）增强接收器抖动存在频率偏离标称速率的串行数据的周期抖动的容限以及标称频率由扩频时钟调制的串行数据。

19. 发明申请

US20070002992A1 Method and apparatus for automatic clock alignment 有权
标题翻译：自动时钟对准的方法和装置
公开(公告)号：US20070002992A1
公开(公告)日：2007-01-04
申请号：US11174228
申请日：2005-07-01
申请人： Vladimir Sindalovsky , Lane Smith
发明人： Vladimir Sindalovsky , Lane Smith
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0814 , H04L7/0337
摘要： The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points Si and transition sampling points Ti. In particular, these offsets are controlled by both coarse and fine adjustments. Typically CDR circuits employ feedback phase control information being supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner.
摘要翻译：本发明使在不同时钟域中产生和使用的信号同步。本发明可应用于CDR电路，其中通过从相对于数据采样点S 1和N 2的转换采样点控制来自PLL频率的相位偏移来实现多相时钟到输入数据相位的相位调整 T 。特别地，这些偏移由粗调和微调两者来控制。通常，CDR电路使用提供给VCDL的反馈相位控制信息。上述调整导致这些相位控制信号具有与PLL时钟的任意和时变关系。通过适当地选择PLL时钟信号的适当边沿，本发明将这些相位控制信号同步到PLL时钟域中，以便以同步方式应用VCDL控制。

20. 发明申请

US20060176943A1 Serializer deserializer (SERDES) testing 有权
公开(公告)号：US20060176943A1
公开(公告)日：2006-08-10
申请号：US11051801
申请日：2005-02-04
申请人： Vladimir Sindalovsky , Lane Smith
发明人： Vladimir Sindalovsky , Lane Smith
IPC分类号： H04B17/00
CPC分类号： G01R31/31716
摘要： The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serialize data communication channel and an input of a deserialize data communication channel to provide a serial data loop-back connection and coupling an output of a deserialize data communication channel and an input of a serialize data communication channel to provide a parallel data loop-back connection. Input test data is provided to a first serialize or deserialize data communication channel, and is successively serialized and deserialized through each corresponding serialize data communication channel and deserialize data communication channel to provide output test data. The output test data and the input test data are then compared, with SERDES devices having acceptable or unacceptable bit error rates respectively designated as passed or failed.

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