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11. 发明授权

US06678643B1 Event based semiconductor test system 失效
标题翻译：基于事件的半导体测试系统
公开(公告)号：US06678643B1
公开(公告)日：2004-01-13
申请号：US09340371
申请日：1999-06-28
申请人： James Alan Turnquist , Shigeru Sugamori , Hiroaki Yamoto
发明人： James Alan Turnquist , Shigeru Sugamori , Hiroaki Yamoto
IPC分类号： G06F1100
CPC分类号： G01R31/318314 , G01R31/318307 , G01R31/318342
摘要： A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.
摘要翻译：一种半导体测试系统，其生成基于在用于在电子设计自动化（EDA）环境中设计的LSI设备的计算机上执行的器件逻辑模拟的数据生成的测试图案，测试LSI器件，并将测试结果反馈给EDA 环境。半导体测试系统包括用于存储通过在被测LSI的设计阶段执行设备逻辑仿真获得的事件数据的事件文件; 事件存储器，用于存储事件文件相对于定时的事件数据; 用于通过直接使用来自事件存储器的事件数据并将测试图案应用于被测试的LSI设备来产生测试图案的装置; 用于评估所测试的LSI设备的响应输出并存储所得到的评估数据的结果数据文件; 以及用于基于存储在结果数据文件中的数据来评估LSI设备的设计的装置。

12. 发明授权

US06631340B2 Application specific event based semiconductor memory test system 失效
标题翻译：基于应用特定事件的半导体存储器测试系统
公开(公告)号：US06631340B2
公开(公告)日：2003-10-07
申请号：US09981535
申请日：2001-10-15
申请人： Shigeru Sugamori , Koji Takahashi , Hiroaki Yamoto
发明人： Shigeru Sugamori , Koji Takahashi , Hiroaki Yamoto
IPC分类号： G01M1900
CPC分类号： G11C29/56
摘要： A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory, a test system main frame to accommodate a combination of the tester modules and the ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.
摘要翻译：用于测试半导体器件的半导体测试系统具有多个不同的测试器模块和用于产生特定于预期存储器的算法模式的算法模式发生器（ALPG），从而实现低成本和专用存储器测试系统。半导体测试系统包括两个或更多个性能彼此不同的测试器模块，用于产生特定于存储器的算法模式的ALPG模块，用于容纳测试器模块和ALPG模块的组合的测试系统主框架，用于电连接测试器模块和被测器件的测试夹具，在测试夹具上提供的用于安装被测器件的性能板，以及用于通过与测试器模块通信来控制测试系统的整体操作的主计算机通过测试总线。

13. 发明授权

US06331770B1 Application specific event based semiconductor test system 失效
标题翻译：基于特定应用事件的半导体测试系统
公开(公告)号：US06331770B1
公开(公告)日：2001-12-18
申请号：US09547753
申请日：2000-04-12
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R700
CPC分类号： G01R31/31724 , G01R31/3167 , G01R31/3187 , G01R31/31905 , G01R31/31921 , G01R31/31922
摘要： A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules in a main frame and a measurement module unique to the device under test in a test fixture, thereby achieving a low cost and application specific test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test system main frame to accommodate a combination of two or more tester modules, a test fixture provided on the main frame for electrically connecting the tester modules and a device under test, a measurement module provided in the test fixture for converting signals between the device under test and the tester module depending on the function of the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.
摘要翻译：一种用于测试半导体器件的半导体测试系统，特别是涉及一种半导体测试系统，该半导体测试系统在主框架中具有多个不同类型的测试器模块，以及在测试夹具中对被测器件特有的测量模块，从而实现了低成本和应用程序特定的测试系统。半导体测试系统包括两个或更多个性能彼此不同的测试器模块，用于容纳两个或更多个测试器模块的组合的测试系统主框架，设置在主框架上用于电连接测试器模块的测试夹具和被测设备，设置在测试夹具中的测量模块，用于根据所测试的设备的功能，在被测设备和测试器模块之间转换信号;以及主计算机，用于通过与测试系统的通信进行通信来控制测试系统的整体操作测试仪模块通过测试仪总线。

14. 发明授权

US4497056A IC Tester 失效
标题翻译： IC测试仪
公开(公告)号：US4497056A
公开(公告)日：1985-01-29
申请号：US407872
申请日：1982-08-13
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319 , H01L21/66
CPC分类号： G01R31/3191
摘要： An IC tester supplies test pattern signal to an IC being tested and compares response signals therefrom with an expected-value pattern signal to determine whether the IC is acceptable or not. During the test, the IC being tested is severed by a separator means from the drivers, for producing the test pattern signals with a timing signal generator set in a condition for generating reference signals. The reference signals and the outputs from the drivers are compared for phase by a phase comparator means. Variable delay means inserted in the paths of the test pattern signal are adjusted by the result of the comparison to suppress skews between the paths of the test pattern signals. Skews in strobe signals, which serve to determine the logic levels of the response signals output from the IC being tested, are also suppressed.
摘要翻译： IC测试器将测试图形信号提供给正在测试的IC，并将其中的响应信号与预期值图案信号进行比较，以确定IC是否可接受。在测试期间，被测试的IC被来自驱动器的分离器装置切断，以便在产生参考信号的条件下用定时信号发生器产生测试图形信号。驱动器的参考信号和输出通过相位比较器进行相位比较。通过比较结果调整插入在测试图形信号的路径中的可变延迟装置，以抑制测试图形信号的路径之间的偏差。用于确定从所测试的IC输出的响应信号的逻辑电平的选通信号中的偏移也被抑制。

15. 发明授权

US06536006B1 Event tester architecture for mixed signal testing 失效
标题翻译：用于混合信号测试的事件测试仪架构
公开(公告)号：US06536006B1
公开(公告)日：2003-03-18
申请号：US09439865
申请日：1999-11-12
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G01R31/3167
摘要： A semiconductor test system having a plurality of different types of tester modules for testing a mixed signal integrated circuit (IC) having analog signals and digital signals with high speed and high efficiency. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules, means provided on the test head for electrically connecting the tester modules and a device under test, an optional circuit corresponding to the device under test when the device under test is a mixed signal IC, and a host computer for controlling an overall operation of the test system. Each event tester module includes a tester board which is configured as an event based tester.
摘要翻译：一种具有多个不同类型的测试器模块的半导体测试系统，用于测试具有高速和高效率的具有模拟信号和数字信号的混合信号集成电路（IC）。半导体测试系统包括两个或更多个性能彼此不同的测试器模块，用于容纳两个或更多个测试器模块的测试头，设置在测试头上用于电连接测试器模块和被测器件的装置，可选当被测设备是混合信号IC时对应于被测设备的电路，以及用于控制测试系统的整体操作的主计算机。每个事件测试器模块包括被配置为基于事件的测试器的测试器板。

16. 发明授权

US06314034B1 Application specific event based semiconductor memory test system 失效
标题翻译：基于应用特定事件的半导体存储器测试系统
公开(公告)号：US06314034B1
公开(公告)日：2001-11-06
申请号：US09549734
申请日：2000-04-14
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G11C700
CPC分类号： G11C29/56
摘要： A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory in the device under test, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory; a test system main frame to accommodate a combination of tester module and ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.
摘要翻译：用于测试半导体器件的半导体测试系统具有多个不同的测试器模块和用于产生特定于被测器件中的预期存储器的算法模式的算法模式发生器（ALPG），从而实现低成本和专用存储器测试系统。半导体测试系统包括两个或更多个性能彼此不同的测试器模块，用于产生特定于存储器的算法模式的ALPG模块; 测试系统主框架，用于容纳测试器模块和ALPG模块的组合，用于电连接测试器模块和被测设备的测试夹具，在测试夹具上提供的用于安装被测器件的性能板，以及主机用于通过通过测试器总线与测试器模块通信来控制测试系统的整体操作。

17. 发明授权

US06185708B2 Maintenance free test system 有权
标题翻译：免维护测试系统
公开(公告)号：US06185708B2
公开(公告)日：2001-02-06
申请号：US09200909
申请日：1998-11-27
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G01R31/31908 , G01R31/31905 , G01R31/31926
摘要： A test system for testing a semiconductor device by having a number of test channels (tester pins) corresponding to the number of terminal pins of the semiconductor device to be tested includes: a tester controller for controlling various operations in the tests system including test patterns to be applied to the device under test, timings and waveforms of the test patterns; a test unit for generating the test patterns and expected value patterns with predetermined timings based on control signals from the tester controller; a pin assignment converter provided between the tester controller and the test unit for providing conversion data showing a conversion relationship between physical pin numbers of the test unit and supplemental tester pin numbers which have been replaced with defective tester pins to the test unit; a test head having drivers for supplying the test patterns from the test unit to the semiconductor device with predetermined amplitudes and comparators for detecting levels of output signals from the semiconductor device and comparing the output level with the expected value; a switch circuit provided between the test head and the semiconductor device for changing the defective tester pin to the supplemental tester pin based on the conversion data from the pin assignment converter; and a system monitor for monitoring the change in the tester pins in the test system and other changes involving maintenance works and managing the data thereof.
摘要翻译：一种用于测试半导体器件的测试系统，该测试系统具有对应于要测试的半导体器件的端子引脚数目的多个测试通道（测试器引脚），包括：测试器控制器，用于控制测试系统中的各种操作，包括测试模式应用于被测设备，测试图案的时序和波形; 测试单元，用于基于来自测试器控制器的控制信号，以预定的定时产生测试图案和预期值图案; 一个引脚分配转换器，设置在测试器控制器和测试单元之间，用于提供转换数据，该转换数据显示测试单元的物理引脚与补充测试器引脚号之间的转换关系，已经被测试单元的缺陷测试器引脚替换; 测试头，其具有用于从测试单元向具有预定幅度的半导体器件提供测试图案的驱动器和用于检测来自半导体器件的输出信号的电平并将输出电平与期望值进行比较的比较器; 设置在所述测试头和所述半导体器件之间的开关电路，用于根据所述引脚分配转换器的转换数据将所述有缺陷的测试器引脚改变为所述补充测试器引脚; 以及用于监视测试系统中的测试器引脚的变化的系统监视器以及涉及维护工作的其他变化以及管理其数据。

18. 发明授权

US07209849B1 Test system, added apparatus, and test method 失效
标题翻译：测试系统，附加仪器和测试方法
公开(公告)号：US07209849B1
公开(公告)日：2007-04-24
申请号：US11393379
申请日：2006-03-30
申请人： Yuya Watanabe , Shigeru Sugamori
发明人： Yuya Watanabe , Shigeru Sugamori
IPC分类号： G01R31/28
CPC分类号： G01R31/31919 , G01R31/31922
摘要： There is provided a test system that tests a device under test. The test system includes a test apparatus that tests the device under test on the basis of an event, and an added apparatus that is added between the device under test and the test apparatus when an interval to which a device output signal is changed is smaller than an interval capable of being processed by the test apparatus, and the added apparatus includes a signal input section that inputs the device output signal output from the device under test according to the device input signal, a change detecting section that detects whether the input device output signal has been changed or not, a change timing detecting section that detects the change timing for the device output signal, a storing section that sequentially stores the change timing and the signal value after the change for the device output signal as an output event, according to the fact that the device output signal has been changed, and a reading section that sequentially reads the output events from the storing section to input the events into the test apparatus.
摘要翻译：提供了测试被测设备的测试系统。该测试系统包括一个测试装置，该测试装置根据一个事件来测试被测设备，并且当一个设备输出信号改变的间隔小于一个时，被添加在被测设备和测试装置之间的附加装置能够由所述测试装置处理的间隔，所述附加装置包括：信号输入部，其输入根据所述装置输入信号从被测设备输出的装置输出信号;变化检测部，其检测所述输入装置输出信号已经改变了，改变定时检测部分检测设备输出信号的改变定时，存储部分将设备输出信号的改变之后的改变定时和信号值顺序地存储为输出事件，根据涉及设备输出信号已被改变的事实，以及从存储部分顺序读取输出事件的读取部分以将事件输入到测试设备中。

19. 发明授权

US06545460B2 Power source current measurement unit for semiconductor test system 失效
标题翻译：半导体测试系统的电源电流测量单元
公开(公告)号：US06545460B2
公开(公告)日：2003-04-08
申请号：US10066870
申请日：2002-02-04
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R3136
CPC分类号： G01R31/31921 , G01R31/3004 , G01R31/3191
摘要： A power source current measurement unit provided in a semiconductor test system measures a power source current of a device under test with high speed and accuracy. The power source measurement unit includes a DA converter for generating a source voltage, an operational amplifier for supplying a power source current to the device under test, a voltage amplifier for amplifying a voltage representing the amount of power source current supplied to the device under test, an integration circuit for accumulating an output signal of the voltage amplifier for a predetermined integration time, and an AD converter for converting an output signal of the integration circuit to a digital signal after the integration time.
摘要翻译：设置在半导体测试系统中的电源电流测量单元以高速度和精度测量被测器件的电源电流。电源测量单元包括用于产生源电压的DA转换器，用于向被测器件提供电源电流的运算放大器，用于放大表示供给到被测器件的电源电流量的电压的电压放大器用于累积电压放大器的输出信号达到预定积分时间的积分电路和用于在积分时间之后将积分电路的输出信号转换为数字信号的AD转换器。

20. 发明授权

US06172544B2 Timing signal generation circuit for semiconductor test system 失效
标题翻译：用于半导体测试系统的定时信号发生电路
公开(公告)号：US06172544B2
公开(公告)日：2001-01-09
申请号：US09257907
申请日：1999-02-25
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： H03Q514
CPC分类号： G01R31/31922
摘要： A timing signal generation circuit to be used in a semiconductor test system which is not affected by voltage changes or temperature changes. The timing signal generation circuit includes a first reference clock, a coarse delay circuit provided with the first reference clock for generating a coarse delay signal having a delay time of an integer multiple of one cycle of the first reference clock on the basis of coarse delay data provided thereto, a second reference clock having a frequency which is predetermined times higher than that of the first reference clock, a first fine delay circuit provided with the second reference clock for producing a fine delay time which is an integer multiple of one cycle of the second reference clock but is smaller than the one cycle of the first reference clock, a selector circuit for selectively applying the coarse delay signal to the first fine delay circuit at an input specified by a select signal, and a second fine delay circuit for receiving an output signal of the first fine delay circuit and adding a delay time which is smaller than the one cycle of the second reference clock to the output signal based on fine delay data. The coarse delay circuit and the second fine delay circuit are formed in a first semiconductor integrated circuit while the first fine delay circuit and the selector circuit are formed in a second semiconductor integrated circuit which has a higher operation speed than that of the first semiconductor integrated circuit.
摘要翻译：一种定时信号发生电路，用于不受电压变化或温度变化影响的半导体测试系统。定时信号产生电路包括第一参考时钟，粗略延迟电路，设置有第一参考时钟，用于基于粗延迟数据产生具有第一参考时钟的一个周期的整数倍的延迟时间的粗延迟信号提供具有比第一参考时钟的频率高预定次数的频率的第二参考时钟;第一精细延迟电路，设置有第二参考时钟，用于产生作为第一参考时钟的一个周期的整数倍的精细延迟时间第二参考时钟，但是小于第一参考时钟的一个周期;选择器电路，用于在由选择信号指定的输入处选择性地将粗延迟信号施加到第一精细延迟电路;以及第二精细延迟电路，输出第一精细延迟电路的输出信号，并将比第二参考时钟的一个周期小的延迟时间加到ou 基于精细延迟数据的输入信号。粗略延迟电路和第二精细延迟电路形成在第一半导体集成电路中，而第一精细延迟电路和选择器电路形成在具有比第一半导体集成电路高的操作速度的第二半导体集成电路中。

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