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11. 发明授权

US08604857B2 Power supply-insensitive buffer and oscillator circuit 有权
标题翻译：电源不敏感缓冲器和振荡器电路
公开(公告)号：US08604857B2
公开(公告)日：2013-12-10
申请号：US13294025
申请日：2011-11-10
申请人： William James Dally
发明人： William James Dally
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： One embodiment of the present invention sets forth a technique for reducing jitter caused by changes in a power supply for a clock generated by a ring oscillator of inverter devices. An inverter sub-circuit is coupled in parallel with a current-starved inverter sub-circuit to produce an inverter circuit that is insensitive to changes in the power supply voltage. When the ring oscillator is used as the voltage controlled oscillator of a phase locked loop, the delay of the inverters may be controlled by varying a bias current for each inverter in response to changes in the power supply voltage to reduce any jitter in a clock output produced by the changes in the power supply voltage. When the transistor devices are sized appropriately and the bias current is adjusted, the sensitivity of the inverter circuit to changes in the power supply voltage may be reduced.
摘要翻译：本发明的一个实施例提出了一种用于减少由逆变器装置的环形振荡器产生的时钟的电源的变化引起的抖动的技术。逆变器子电路与电流欠压逆变器子电路并联耦合，以产生对电源电压变化不敏感的逆变器电路。当环形振荡器用作锁相环的压控振荡器时，可以通过响应于电源电压的变化改变每个逆变器的偏置电流来控制反相器的延迟，以减少时钟输出中的任何抖动由电源电压的变化产生。当晶体管器件的尺寸适当并且调节偏置电流时，可以减小逆变器电路对电源电压变化的灵敏度。

12. 发明授权

US08024553B2 Data exchange and communication between execution units in a parallel processor 有权
标题翻译：并行处理器中执行单元之间的数据交换和通信
公开(公告)号：US08024553B2
公开(公告)日：2011-09-20
申请号：US12192813
申请日：2008-08-15
申请人： Brucek Khailany , William James Dally , Ujval J. Kapasi , Jim Jian Lin
发明人： Brucek Khailany , William James Dally , Ujval J. Kapasi , Jim Jian Lin
IPC分类号： G06F9/44 , G06F15/76
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3891
摘要： A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.
摘要翻译：一种具有多个执行通道的集成电路处理装置内的操作方法。在接收到在执行通道之间交换数据的指令时，检查来自执行通道的相应请求，以确定在第一间隔期间可以将数据发送到执行通道的一个或多个其他执行通道的集合。用信号通知执行通道集合内的每个执行通道，以指示执行通道可以向执行通道中的一个或其他执行通道发送数据。

13. 发明授权

US08788761B2 System and method for explicitly managing cache coherence 有权
标题翻译：明确管理缓存一致性的系统和方法
公开(公告)号：US08788761B2
公开(公告)日：2014-07-22
申请号：US13243948
申请日：2011-09-23
申请人： William James Dally
发明人： William James Dally
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0842
摘要： One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.
摘要翻译：本发明的一个实施例阐述了对具有两个显式控制状态P（私有）和R（只读））的高速缓存一致性协议的扩展，其提供对程序逻辑可以保证正确的高速缓存行的显式程序控制行为。在私有状态下，只有高速缓存行的所有者可以访问高速缓存行进行读取或写入操作。在只读状态下，只能对高速缓存线执行读操作，从而不允许执行写操作。

14. 发明授权

US08412917B2 Data exchange and communication between execution units in a parallel processor 有权
标题翻译：并行处理器中执行单元之间的数据交换和通信
公开(公告)号：US08412917B2
公开(公告)日：2013-04-02
申请号：US13237646
申请日：2011-09-20
申请人： Brucek Khailany , William James Dally , Ujval J. Kapasi , Jim Jian Lin
发明人： Brucek Khailany , William James Dally , Ujval J. Kapasi , Jim Jian Lin
IPC分类号： G06F9/00
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3891
摘要： Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.
摘要翻译：公开了用于动态地确定数据传送路径的方法和系统。响应于便于执行并行操作的集成电路处理装置中的执行通道之间的数据传送的指令来动态地确定数据传送路径。此外，实施例包括可并行执行操作的集成电路处理设备，包括向潜在源通道提供确认信息的能力，所述确认信息指示潜在源通道是否可以在数据通路期间向所请求的目的地通道发送数据，传输间隔。

15. 发明授权

US08122078B2 Processor with enhanced combined-arithmetic capability 有权
标题翻译：具有增强的组合算术能力的处理器
公开(公告)号：US08122078B2
公开(公告)日：2012-02-21
申请号：US11973887
申请日：2007-10-09
申请人： Brucek Khailany , William James Dally , Raghunath Rao , DeForest Tovey
发明人： Brucek Khailany , William James Dally , Raghunath Rao , DeForest Tovey
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3891
摘要： A method of operation within an integrated-circuit processing device having an enhanced combined-arithmetic capability. In response to an instruction indicating a combined arithmetic operation, the processor generates a dot-product of first and second operands, adds the dot-product to an accumulated value, and then outputs the sum of the accumulated value and the dot-product.
摘要翻译：具有增强的组合算术能力的集成电路处理装置内的操作方法。响应于指示组合算术运算的指令，处理器产生第一和第二操作数的点乘积，将点积加到累加值，然后输出累积值和点积的和。

16. 发明申请

US20120079201A1 SYSTEM AND METHOD FOR EXPLICITLY MANAGING CACHE COHERENCE 有权
标题翻译：用于显式管理高速缓存的系统和方法
公开(公告)号：US20120079201A1
公开(公告)日：2012-03-29
申请号：US13243948
申请日：2011-09-23
申请人： William James Dally
发明人： William James Dally
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0842
摘要： One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.
摘要翻译：本发明的一个实施例阐述了对具有两个显式控制状态P（私有）和R（只读））的高速缓存一致性协议的扩展，其提供对程序逻辑可以保证正确的高速缓存行的显式程序控制行为。在私有状态下，只有高速缓存行的所有者可以访问高速缓存行进行读取或写入操作。在只读状态下，只能对高速缓存线执行读操作，从而不允许执行写操作。

17. 发明申请

US20080307207A1 DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR 有权
标题翻译：并行处理器中执行单位之间的数据交换和通信
公开(公告)号：US20080307207A1
公开(公告)日：2008-12-11
申请号：US12192813
申请日：2008-08-15
申请人： Brucek Khailany , William James Dally , Ujval J. Kapasi , Jim Jian Lin
发明人： Brucek Khailany , William James Dally , Ujval J. Kapasi , Jim Jian Lin
IPC分类号： G06F9/30
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3891
摘要： A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.
摘要翻译：一种具有多个执行通道的集成电路处理装置内的操作方法。在接收到在执行通道之间交换数据的指令时，检查来自执行通道的相应请求，以确定在第一间隔期间可以将数据发送到执行通道的一个或多个其他执行通道的集合。用信号通知执行通道集合内的每个执行通道，以指示执行通道可以向执行通道中的一个或其他执行通道发送数据。

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