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11. 发明授权

US06427224B1 Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor 失效
标题翻译：有效验证包括嵌入式处理器在内的片上系统集成电路设计的方法
公开(公告)号：US06427224B1
公开(公告)日：2002-07-30
申请号：US09494564
申请日：2000-01-31
申请人： Robert J. Devins , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. The partitioning of the verification software as described above allows for a “split-domain” mode of verification in which only the low-level code is executed by a simulated processor model, while the rest of the code executes externally to the simulator. Because most of the verification software executes externally to the simulator while only the low-level code executes on the simulated processor, the overhead of performing the high-level functions is removed from the simulator. As a result, faster verification is enabled.
摘要翻译：一种使用验证软件来测试包括嵌入式处理器在内的片上系统（SOC）设计的方法。验证软件用于生成和应用测试用例，以刺激模拟中的SOC设计; 观察结果并用于对设计进行设计。包括嵌入式处理器的SOC设计的验证通常非常慢。为了在这种情况下提供加速验证模式，在本发明的方法中，验证软件被分为更高级别的控制代码和较低级别的设备驱动程序代码。上级代码执行决策，测试初始化，测试随机化，多任务处理以及测试结果与预期结果的比较等功能。低级代码接口与核心正在被模拟，以便在硬件级别的操作上应用上层代码生成的测试用例。如上所述的验证软件的划分允许“分割域”验证模式，其中只有低级代码由模拟处理器模型执行，而其余代码在模拟器外部执行。因为大多数验证软件在模拟器外部执行，而仅在模拟处理器上执行低级代码，所以执行高级功能的开销从模拟器中移除。因此，启用更快的验证。

12. 发明授权

US07917348B2 Method of switching external models in an automated system-on-chip integrated circuit design verification system 有权
标题翻译：在自动系统级芯片集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US07917348B2
公开(公告)日：2011-03-29
申请号：US11969991
申请日：2008-01-07
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统和方法。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

13. 发明授权

US07729877B2 Method and system for logic verification using mirror interface 失效
标题翻译：使用镜像接口进行逻辑验证的方法和系统
公开(公告)号：US07729877B2
公开(公告)日：2010-06-01
申请号：US11930820
申请日：2007-10-31
申请人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译：核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。通常，标准化模型提供比所需更多的功能。可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。本发明提供了一种有效和经济的替代方案。经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。

14. 发明授权

US07451070B2 Optimal bus operation performance in a logic simulation environment 有权
标题翻译：逻辑仿真环境中最优总线运算性能
公开(公告)号：US07451070B2
公开(公告)日：2008-11-11
申请号：US10907628
申请日：2005-04-08
申请人： Robert J. Devins , David W. Milton
发明人： Robert J. Devins , David W. Milton
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
摘要翻译：来自总线功能模型和二进制收敛算法的采样计数反馈是为加速器或硬件辅助模拟器生成最佳采样值。模拟器包括总线功能模型和驱动程序。软件可读寄存器维持在总线功能模型上执行交易的模拟器提供的多个样本的计数。对于每个支持的总线功能模型，维护从总线功能模型检索的样本计数和给定硬件辅助仿真器的最后一个采样值，并应用二进制收敛算法，以根据给予硬件辅助的最后一个采样值来生成采样值模拟器和给定总线功能模型用于交易的最后一个实际采样值。

15. 发明授权

US07353156B2 Method of switching external models in an automated system-on-chip integrated circuit design verification system 有权
标题翻译：在自动系统级芯片集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US07353156B2
公开(公告)日：2008-04-01
申请号：US09683677
申请日：2002-02-01
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

16. 发明授权

US07353131B2 Method and system for logic verification using mirror interface 有权
标题翻译：使用镜像接口进行逻辑验证的方法和系统
公开(公告)号：US07353131B2
公开(公告)日：2008-04-01
申请号：US10986773
申请日：2004-11-15
申请人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译：核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。通常，标准化模型提供比所需更多的功能。可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。本发明提供了一种有效和经济的替代方案。经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。

17. 发明授权

US5784595A DMA emulation for non-DMA capable interface cards 失效
标题翻译：非DMA能力接口卡的DMA仿真
公开(公告)号：US5784595A
公开(公告)日：1998-07-21
申请号：US908214
申请日：1997-08-07
申请人： Robert J. Devins , Stephen Hon , Patrick Kam , Emory D. Keller
发明人： Robert J. Devins , Stephen Hon , Patrick Kam , Emory D. Keller
IPC分类号： G06F9/455 , G06F13/10 , G06F13/28 , G06F31/00 , G06F13/32
CPC分类号： G06F9/45537 , G06F13/105 , G06F13/28
摘要： A method and system are disclosed for simulating a direct memory access (DMA) function to access memory in a host computer having a DMA controller for the purpose of enabling the transfer of data between the host memory and a computer accessory data handling device not capable of DMA operation. The accessory data handling device can be operably connected to the host. The address contents of the DMA controller can be read to determine the location in the host memory where data is to be transferred from the host memory to the accessory data handling device or from the accessory data handling device to the host memory. Data is read from the host memory at the address specified in the DMA controller and written to the accessory data handling device or read from the accessory data handling device and written to the host memory at the address specified by the DMA controller, respectively. The host computer is informed that a DMA operation corresponding to the data transfer has been completed when the data transfer required has been completed.
摘要翻译：公开了一种用于模拟直接存储器访问（DMA）功能以访问具有DMA控制器的主计算机中的存储器的方法和系统，以便能够在主机存储器和不能够执行以下操作的计算机辅助数据处理设备之间传输数据 DMA操作。附件数据处理装置可以可操作地连接到主机。可以读取DMA控制器的地址内容，以确定主机存储器中要从主机存储器传输到附件数据处理设备或从附件数据处理设备传输到主机存储器的位置。数据从DMA控制器中指定的地址从主机存储器读取，并写入附件数据处理设备或从附件数据处理设备读取，并分别以DMA控制器指定的地址写入主机存储器。当完成数据传输时，主计算机通知对应于数据传输的DMA操作已经完成。

18. 发明授权

US08234624B2 System and method for developing embedded software in-situ 有权
标题翻译：原位开发嵌入式软件的系统和方法
公开(公告)号：US08234624B2
公开(公告)日：2012-07-31
申请号：US11626967
申请日：2007-01-25
申请人： Robert J. Devins , Nagashyamala R. Dhanwada
发明人： Robert J. Devins , Nagashyamala R. Dhanwada
IPC分类号： G06F9/44
CPC分类号： G06F17/505
摘要： A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.
摘要翻译：用于开发新外设硬件的新外设软件开发系统，将用于新的集成系统。开发系统包括与新集成系统基本相同的遗留或预先存在的集成系统。制作了新的外设硬件的型号。模型的每个I / O寄存器映射到内存映射的I / O空间。对应于新的外围设备软件代码的开发代码在预先存在的硬件上执行，以便通过存储器映射的I / O空间与模型进行交互。在一个实施例中，该模型作为预先存在的集成系统上的嵌入式模型来执行。在另一个实施例中，该模型作为非嵌入式模型被执行在硬件描述语言模拟器上。

19. 发明申请

US20080184193A1 SYSTEM AND METHOD FOR DEVELOPING EMBEDDED SOFTWARE IN-SITU 有权
标题翻译：用于开发嵌入式软件的系统和方法
公开(公告)号：US20080184193A1
公开(公告)日：2008-07-31
申请号：US11626967
申请日：2007-01-25
申请人： Robert J. Devins , Nagashyamala R. Dhanwada
发明人： Robert J. Devins , Nagashyamala R. Dhanwada
IPC分类号： G06F9/44
CPC分类号： G06F17/505
摘要： A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.
摘要翻译：用于开发新外设硬件的新外设软件开发系统，将用于新的集成系统。开发系统包括与新集成系统基本相同的遗留或预先存在的集成系统。制作了新的外设硬件的型号。模型的每个I / O寄存器映射到内存映射的I / O空间。对应于新的外围设备软件代码的开发代码在预先存在的硬件上执行，以便通过存储器映射的I / O空间与模型进行交互。在一个实施例中，该模型作为预先存在的集成系统上的嵌入式模型来执行。在另一个实施例中，该模型作为非嵌入式模型被执行在硬件描述语言模拟器上。

20. 发明授权

US06762761B2 Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions 有权
公开(公告)号：US06762761B2
公开(公告)日：2004-07-13
申请号：US09283387
申请日：1999-03-31
申请人： Robert J. Devins , Paul M. Schanely
发明人： Robert J. Devins , Paul M. Schanely
IPC分类号： G06F1516
CPC分类号： G06T15/005
摘要： A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

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