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11. 发明授权

US06809396B2 Integrated circuit with a high speed narrow base width vertical PNP transistor 有权
标题翻译：具有高速窄基极宽垂直PNP晶体管的集成电路
公开(公告)号：US06809396B2
公开(公告)日：2004-10-26
申请号：US10303168
申请日：2002-11-25
申请人： Peter J. Zdebel , Misbahul Azam , Gary H. Loechelt , James R. Morgan , Julio C. Costa
发明人： Peter J. Zdebel , Misbahul Azam , Gary H. Loechelt , James R. Morgan , Julio C. Costa
IPC分类号： H01L2973
CPC分类号： H01L21/82285 , H01L27/0826
摘要： An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).
摘要翻译：集成电路（100）包括高性能互补双极NPN和PNP垂直晶体管（10,20）。 NPN晶体管形成在其表面（24）被掺杂以形成PNP基极区域（28,70）的半导体衬底上。在该表面上形成一个薄膜（32,34,30），该开口（42）位于基部区域的边缘上。沿着开口的第一侧壁（78）形成第一导电间隔物（48），以在基极区域内限定PNP发射极区域（67）。第二导电间隔物（47）沿着开口的第二侧壁（76）形成以限定PNP收集区（66）。

12. 发明授权

US5965930A High frequency bipolar transistor and method of forming the same 失效
标题翻译：高频双极晶体管及其形成方法
公开(公告)号：US5965930A
公开(公告)日：1999-10-12
申请号：US964001
申请日：1997-11-04
申请人： Kurt K. Sakamoto , Peter J. Zdebel , Michael G. Lincoln
发明人： Kurt K. Sakamoto , Peter J. Zdebel , Michael G. Lincoln
IPC分类号： H01L29/73 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/732
CPC分类号： H01L29/0821 , H01L29/0649 , H01L29/7322 , H01L2224/05554 , H01L2224/48237 , H01L2924/1305 , H01L2924/30107 , H01L2924/3011
摘要： A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.
摘要翻译：在衬底（61）上形成具有减小的电容和电感的高频双极晶体管（30,60）。衬底（61）被重掺杂以形成低电阻电流通路。轻掺杂的外延层（62）将衬底（61）与形成晶体管的层分离。外延层（62）与基板（61）的导电类型相同。顶侧衬底接触（73）将晶体管（60）的发射极耦合到衬底（61）。基板（61）的背面被金属化并且导电地附接到引线框架（51）的引线标记，从而消除晶体管的发射极中的引线键合电感。

13. 发明授权

US5920095A Short channel field effect semiconductor device and method of making 失效
标题翻译：短沟道场效应半导体器件及其制造方法
公开(公告)号：US5920095A
公开(公告)日：1999-07-06
申请号：US903080
申请日：1997-07-30
申请人： Robert Bruce Davies , Peter J. Zdebel
发明人： Robert Bruce Davies , Peter J. Zdebel
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/762 , H01L23/485 , H01L29/417 , H01L29/423 , H01L29/49 , H01L27/01
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/762 , H01L23/485 , H01L29/41766 , H01L29/41775 , H01L29/42376 , H01L29/66606 , H01L29/66636 , H01L21/2257 , H01L29/4925 , H01L29/665 , H01L2924/0002
摘要： A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a source region (44) and a drain region (45) that contact the corners (13) of the pedestal structure (16). Electrical connection to the source region (44) and the drain region (45) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).
摘要翻译：半导体器件（10）形成在覆盖半导体衬底（11）的基座结构（16）中。半导体器件（10）包括与基座结构（16）的角部（13）接触的源极区（44）和漏极区（45）。与源极区域（44）和漏极区域（45）的电连接由与基座结构（16）的侧面（12）和拐角（13）接触的导电层（28）提供。

14. 发明授权

US5070031A Complementary semiconductor region fabrication 失效
标题翻译：互补半导体区域制造
公开(公告)号：US5070031A
公开(公告)日：1991-12-03
申请号：US627477
申请日：1990-12-14
申请人： Peter J. Zdebel
发明人： Peter J. Zdebel
IPC分类号： H01L21/22 , H01L21/763 , H01L21/8238
CPC分类号： H01L21/763 , H01L21/2205 , H01L21/823892 , Y10S148/025
摘要： A method of forming oppositely doped semiconductor regions includes providing a first semiconductor layer of a first conductivity type and forming a second semiconductor layer of a second conductivity type on a portion of the first layer. A third semiconductor layer is formed on the second layer and the exposed portions of the first layer. The dopant concentration of the third layer is less than the dopant concentration of the second layer so that dopant of the second conductivity type diffuses from the second layer into the portion of the third layer disposed thereabove.
摘要翻译：形成相对掺杂的半导体区域的方法包括提供第一导电类型的第一半导体层，并在第一层的一部分上形成第二导电类型的第二半导体层。在第二层和第一层的暴露部分上形成第三半导体层。第三层的掺杂剂浓度小于第二层的掺杂剂浓度，使得第二导电类型的掺杂剂从第二层扩散到设置在其上的第三层的部分。

15. 发明授权

US4905070A Semiconductor device exhibiting no degradation of low current gain 失效
标题翻译：不会降低低电流增益的半导体器件
公开(公告)号：US4905070A
公开(公告)日：1990-02-27
申请号：US239879
申请日：1988-09-02
申请人： Israel A. Lesk , Peter J. Zdebel , Han-Bin K. Liang
发明人： Israel A. Lesk , Peter J. Zdebel , Han-Bin K. Liang
IPC分类号： H01L29/73 , H01L29/74
CPC分类号： H01L29/7408 , H01L29/7302
摘要： The degradation of the low current gain, which is exhibited during emitter-base reverse bias breakdown testing, is prevented by providing an emitter-base resistive shunt on the surface. This resistive shunt, preferably made of silicon nitride. utilizes surface recombination to reduce the low current gain permanently, thus a degradation is not exhibited upon testing.
摘要翻译：通过在表面上提供发射极基电阻分流来防止在发射极 - 基极反向偏压击穿测试期间显示的低电流增益的劣化。这种电阻性分流器，优选由氮化硅制成。利用表面复合来永久地降低低电流增益，从而在测试时不会出现劣化。

16. 发明授权

US08299560B2 Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same 有权
标题翻译：包括埋入绝缘层和延伸穿过其的垂直导电结构的电子器件及其形成工艺
公开(公告)号：US08299560B2
公开(公告)日：2012-10-30
申请号：US12702055
申请日：2010-02-08
申请人： Gary H. Loechelt , Gordon M. Grivna , Peter J. Zdebel
发明人： Gary H. Loechelt , Gordon M. Grivna , Peter J. Zdebel
IPC分类号： H01L21/70
CPC分类号： H01L29/66696 , H01L21/26586 , H01L21/2815 , H01L21/743 , H01L21/823475 , H01L27/1203 , H01L29/0626 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1008 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/42376 , H01L29/6625 , H01L29/66659 , H01L29/66689 , H01L29/735 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.
摘要翻译：电子器件可以包括掩埋导电区域，掩埋导电区域上的掩埋绝缘层和设置在掩埋绝缘层上的半导体层，其中半导体层具有主表面和相对表面，并且掩埋导电区域相对于主表面更靠近对置的表面。电子设备还可以包括第一晶体管的载流电极，其中载流电极沿着主表面设置并与掩埋的导电层间隔开。电子器件还可以包括延伸穿过掩埋绝缘层的垂直导电结构，其中垂直导电结构电连接到载流电极和掩埋导电区域。

17. 发明申请

US20110207277A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER 有权
标题翻译：形成具有垂直电荷补偿结构和子表面连接层的半导体器件的方法
公开(公告)号：US20110207277A1
公开(公告)日：2011-08-25
申请号：US13099157
申请日：2011-05-02
申请人： Gary H. Loechelt , Peter J. Zdebel
发明人： Gary H. Loechelt , Peter J. Zdebel
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.
摘要翻译：在一个实施例中，形成具有垂直局部电荷补偿沟槽，沟槽控制区和次表面掺杂层的半导体器件。垂直局部电荷补偿沟槽包括至少一对相反的导电型半导体层。沟槽控制区域被配置为提供将源极区域电耦合到子表面掺杂层的大致垂直的沟道区域。子表面掺杂层还被配置为将沟道的漏极端电连接到垂直的局部电荷补偿沟槽。主体区域被配置为将子表面掺杂层与器件的表面隔离。

18. 发明授权

US07768078B2 Power semiconductor device having improved performance and method 有权
标题翻译：功率半导体器件具有改进的性能和方法
公开(公告)号：US07768078B2
公开(公告)日：2010-08-03
申请号：US12236947
申请日：2008-09-24
申请人： Gary H. Loechelt , Peter J. Zdebel
发明人： Gary H. Loechelt , Peter J. Zdebel
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L21/2815 , H01L29/0619 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66719 , H01L29/66727 , Y10S257/90
摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.
摘要翻译：在一个实施例中，半导体器件形成在半导体材料体中。半导体器件包括与沟道区间隔开的反掺杂漏极区。

19. 发明授权

US5108946A Method of forming planar isolation regions 失效
标题翻译：形成平面隔离区域的方法
公开(公告)号：US5108946A
公开(公告)日：1992-04-28
申请号：US559460
申请日：1990-07-27
申请人： Peter J. Zdebel , Barbara Vasquez , Hang M. Liaw , Christian A. Seelbach
发明人： Peter J. Zdebel , Barbara Vasquez , Hang M. Liaw , Christian A. Seelbach
IPC分类号： H01L21/74 , H01L21/763
CPC分类号： H01L21/763 , H01L21/743
摘要： A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.
摘要翻译：在半导体结构中形成平面隔离区域的方法包括提供半导体衬底并在其上形成半导体层。包含至少两种不同介电材料的电介质层设置在半导体层上，并且通过其蚀刻沟槽并进入半导体层。介质侧壁形成在沟槽中，然后通过选择性地在其中沉积多晶硅来填充沟槽。然后将半导体材料至少部分地氧化以形成平面隔离区域。本文公开的隔离区域可以用于室内和隔离隔离。

20. 发明授权

US5067002A Integrated circuit structures having polycrystalline electrode contacts 失效
标题翻译：具有多晶电极触点的集成电路结构
公开(公告)号：US5067002A
公开(公告)日：1991-11-19
申请号：US304984
申请日：1989-01-31
申请人： Peter J. Zdebel , Raymond J. Balda , Bor-Yuan Hwang , Allen J. Wagner
发明人： Peter J. Zdebel , Raymond J. Balda , Bor-Yuan Hwang , Allen J. Wagner
IPC分类号： H01L21/033 , H01L21/225 , H01L21/285
CPC分类号： H01L21/033 , H01L21/2257 , H01L21/28525
摘要： A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.
摘要翻译：公开了一种用于制造改进的集成电路器件的工艺。根据本发明的一个实施例，通过在不依赖于限制性光刻公差的情况下产生小的器件区域的工艺来制造集成器件。该方法使用四个多晶硅层来制造和接触器件区域，以实现相对平面的结构，并且将器件区域的尺寸减小到低于正常光刻公差的尺寸。该过程使用主掩模来定义设备的基本占位面积，并与每个光刻步骤中易于对准的封锁掩模相结合。还描述了可以同时制造的诸如互补横向和垂直双极晶体管，JFET，SIT，MOSFET，电阻器，二极管，电容器和其它器件的许多类型器件的手段和方法。

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