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11. 发明授权

US5471511A Digital phase-locked loop arrangement for use in a desynchronizer 失效
标题翻译：用于去同步器的数字锁相环装置
公开(公告)号：US5471511A
公开(公告)日：1995-11-28
申请号：US260771
申请日：1994-06-16
申请人： Marc R. F. De Langhe , Peter P. F. Reusens , Johan J. G. Haspeslagh , Stefaan M. A. Van Hoogenbemt
发明人： Marc R. F. De Langhe , Peter P. F. Reusens , Johan J. G. Haspeslagh , Stefaan M. A. Van Hoogenbemt
IPC分类号： H04J3/07 , H03D3/24 , H04L7/00
CPC分类号： H04J3/076
摘要： A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.
摘要翻译：公开了一种数字锁相环布置，用于去同步器中对来自同步比特流的同步流进行解映射以消除由于同步流引起的开销间隙的抖动。为此，构成同步流的同步比特流的一部分被写入到缓冲存储器（BUFF）中，其写入地址（WRADDR）以该同步部分的速率递增。用于缓冲存储器（BUFF）的读地址（RDADDR）来自数字锁相环布置中的写地址（WRADDR）。这里，提供了同步比特流中的字节对齐的负反馈以及其中的比特对齐的正反馈，使得字节对齐引起读地址（RDADDR）的递增速率的较低变化，但持续时间更长，而位理由导致这种增长率的变化增加，但持续时间更短。

12. 发明授权

US5369669A Data transmission system for synchronously transmitting an auxiliary bitstream within a main bitstream 失效
标题翻译：用于在主比特流内同步发送辅助比特流的数据传输系统
公开(公告)号：US5369669A
公开(公告)日：1994-11-29
申请号：US994827
申请日：1992-12-22
申请人： Jurgen M. E. Tombal , Peter P. F. Reusens , Daniel Sallaerts
发明人： Jurgen M. E. Tombal , Peter P. F. Reusens , Daniel Sallaerts
IPC分类号： H04L25/49 , H04B14/04 , H04J3/12
CPC分类号： H04L25/4925
摘要： A data transmission system is proposed in which an auxiliary bitstream of low bitrate (AUX) is coded together with a main bitstream of high bitrate (PRIM) without increasing the transmission rate above the high bitrate. This auxiliary bitstream (AUX) is moreover transmitted synchronously with the main bitstream (PRIM). Transmitter (T) divides the main bitstream (PRIM) in periodically occurring blocks of Y bits and codes one bit of the auxiliary bitstream (AUX) in each of the blocks by using a first (AMI) or a second (VAMI) coding law according to the binary value of that bit. The second law is constructed by violating the first coding law (AMI) according to a predetermined violation law. Redundancy in the first coding law (AMI) is used to introduce symbol sequences not permitted under this first coding law (AMI) and to so obtain the second coding law (VAMI).
摘要翻译：提出了一种数据传输系统，其中低比特率（AUX）的辅助比特流与高比特率（PRIM）的主比特流一起被编码，而不增加高于高比特率的传输速率。此外，该辅助比特流（AUX）与主比特流（PRIM）同步传输。发射机（T）在周期性发生的Y比特块中划分主比特流（PRIM），并通过使用第一（AMI）或第二（VAMI）编码规则对每个块中的辅助比特流（AUX）的一个比特进行编码到该位的二进制值。第二定律是根据预定违规法违反第一编码法（AMI）构建的。第一编码规则（AMI）中的冗余用于引入该第一编码规则（AMI）下不允许的符号序列，从而获得第二编码规则（VAMI）。

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