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11. 发明授权

US5722162A Fabrication procedure for a stable post 失效
标题翻译：一个稳定的岗位的制作程序
公开(公告)号：US5722162A
公开(公告)日：1998-03-03
申请号：US541219
申请日：1995-10-12
申请人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
IPC分类号： G03F7/26 , H01L21/48 , H01L23/12 , H01L23/52 , H05K3/18 , H05K3/40 , H05K3/10
CPC分类号： H05K3/4007 , H01L21/4853 , H01L2924/00013 , H05K2201/0347 , H05K2201/0367 , H05K2203/0577 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.
摘要翻译：通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱，宽孔径面罩或简单的UV空白洪水曝光。在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。然后可以通过电镀填充该开口以产生强大的整体互连柱。

12. 发明授权

US06248151B1 Method of manufacturing three dimensional parts using an inert gas 有权
标题翻译：使用惰性气体制造三维部件的方法
公开(公告)号：US06248151B1
公开(公告)日：2001-06-19
申请号：US09302929
申请日：1999-04-30
申请人： David A. Horine
发明人： David A. Horine
IPC分类号： B05D102
CPC分类号： C22B4/00 , B05D1/02 , B41J2/14008 , B41J2202/04 , C21C1/00 , C23C4/123 , H05K3/14 , H05K3/3457
摘要： A method for manufacturing metal structures in which minute drops of a liquid metal are emitted from an acoustic device through an inert gas. The presence of the inert gas at the surface of the liquid metal prevent the formation of an oxide skin which would absorb acoustic energy and hinder droplet formation and emission. The droplets are then emitted towards a substrate, which may form as a carrier, where they may be used to form solder bumps, circuit traces, or accepted to form a three dimensional device.
摘要翻译：一种用于制造金属结构的方法，其中液体金属的液滴通过惰性气体从声学装置发射。在液态金属表面存在惰性气体防止氧化皮肤的形成，其将吸收声能并阻止液滴的形成和发射。然后将液滴发射到衬底，衬底可以形成为载体，在衬底中，可以将它们用于形成焊料凸块，电路迹线或被接受以形成三维器件。

13. 发明授权

US06168971A Method of assembling thin film jumper connectors to a substrate 失效
标题翻译：将薄膜跳线连接器组装到基板上的方法
公开(公告)号：US06168971A
公开(公告)日：2001-01-02
申请号：US09072806
申请日：1998-05-05
申请人： David G. Love , Patricia R. Boucher , David A. Horine
发明人： David G. Love , Patricia R. Boucher , David A. Horine
IPC分类号： H01L2144
CPC分类号： H05K3/303 , B23K2101/40 , H01L2224/16 , H05K1/0269 , H05K3/361 , H05K2201/09918 , H05K2203/0173 , H05K2203/085 , H05K2203/166 , Y02P70/613
摘要： A method of assembling thin film jumper connectors to a substrate as part of a process of manufacturing a multi-chip-module or other device having multiple components bonded to chip carrier or other substrate. An alignment plate is positioned on the chuck of a standard flip-chip bonding machine. The thin film jumper connectors are placed on the alignment plate in a face-up position after alignment to alignment marks on the plate using the machine's moveable platform and split-field viewer. The jumper connectors are held to the alignment plate by a force supplied by the vacuum system of the flip-chip bonder, with the force being transmitted to the jumpers through vacuum holes in the alignment plate. The plate's alignment marks are positioned so that when they are aligned with corresponding marks on the connectors, the bonding pads on the connectors are correctly aligned to the pads on the substrate. The substrate or chip carrier is then placed on the moveable platform and rotated to a face-down position. The substrate is moved into a coarse position over the thin film connectors, aligned with the split-field viewer, and then lowered into contact with the contacts of the connectors. The entire assembly, including the alignment plate is then placed in a reflow furnace or otherwise heated to cause the solder bumps on the thin film connector pads to make good electrical contact with the bonding pads on the substrate. Depending on the thermal relationships between the integrated circuit chips, the thin film connectors, and the substrate, the chips may be connected to the substrate either before or after the thin film jumper connectors are bonded to the substrate. If the chips are connected prior to the assembly of the thin film connectors, then a chip cavity is formed in the alignment plate to prevent contact between the chips and the bonding apparatus during the thin film connector bonding.
摘要翻译：将薄膜跳线连接器组装到基板的方法，作为制造具有多个部件的多芯片组件或其它装置的制造方法的一部分，其结合到芯片载体或其它基板上。定位板位于标准倒装芯片接合机的卡盘上。使用机器的可移动平台和分割场观察器将薄膜跳线连接器对准到板上的对准标记之后，面对着位置放置在对准板上。跳线连接器由倒装焊接机的真空系统提供的力保持在对准板上，力通过对准板上的真空孔传递给跳线。板的对准标记被定位成使得当它们与连接器上的相应标记对准时，连接器上的接合焊盘正确地对准衬底上的焊盘。然后将衬底或芯片载体放置在可移动平台上并且旋转到面朝下的位置。衬底移动到薄膜连接器上的粗略位置，与分割场观察器对齐，然后降低成与连接器的触点接触。然后将包括对准板的整个组件放置在回流炉中或以其他方式加热，以使薄膜连接器焊盘上的焊料凸块与衬底上的焊盘良好的电接触。根据集成电路芯片，薄膜连接器和基板之间的热关系，芯片可以在薄膜跨接器连接器结合到基板之前或之后连接到基板。如果在组装薄膜连接器之前将芯片连接，则在对准板中形成芯片空腔，以防止在薄膜连接器接合期间芯片和接合装置之间的接触。

14. 发明授权

US06034332A Power supply distribution structure for integrated circuit chip modules 失效
标题翻译：集成电路芯片模块的电源分配结构
公开(公告)号：US06034332A
公开(公告)日：2000-03-07
申请号：US038805
申请日：1998-03-11
申请人： Larry Louis Moresco , Richard L. Wheeler , Solomon I. Beilin , David A. Horine
发明人： Larry Louis Moresco , Richard L. Wheeler , Solomon I. Beilin , David A. Horine
IPC分类号： H01L23/12 , H01L21/48 , H01L21/822 , H01L23/50 , H01L23/538 , H01L27/01 , H01L27/04 , H05K1/03
CPC分类号： H01L21/4857 , H01L23/50 , H01L2224/16 , H01L2924/3011 , Y10T29/49144
摘要： A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material. A multilayered thin film structure for a multichip module may be formed over the power distribution structure and power and ground potentials supplied to microelectronic components, such as integrated circuit chips, mounted on the surface of the thin film structure using vias routed through the thin film structure.
摘要翻译：包括基板，以图案排列的多个台面的多芯片模块的配电结构形成在基板上，台面具有基本上位于单个平面中的导电上表面。在台面的暴露的侧表面和支撑基底的暴露的表面之上形成薄的共形绝缘层，并且导电材料沉积在填充台面之间并围绕台面的区域的电介质材料上。台面的上表面和围绕台面的导电材料的上表面位于基本上一个平面中并且通过介电材料彼此电隔离。用于多芯片模块的多层薄膜结构可以在功率分配结构上形成，并且提供给微电子部件（例如集成电路芯片）的功率和接地电位，其使用通过薄膜结构布线的通孔安装在薄膜结构的表面上。

15. 发明授权

US5655290A Method for making a three-dimensional multichip module 失效
标题翻译：制造三维多芯片模块的方法
公开(公告)号：US5655290A
公开(公告)日：1997-08-12
申请号：US380083
申请日：1995-01-30
申请人： Larry L. Moresco , David A. Horine , Wen-Chou Vincent Wang
发明人： Larry L. Moresco , David A. Horine , Wen-Chou Vincent Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H05K3/36
CPC分类号： H01L23/4985 , H01L21/486 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/3011 , Y10T29/49126
摘要： A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained. The overall design of the three dimensional structure of the present invention is highly modular to facilitate high yield fabrication and repair.
摘要翻译：示出了用于容纳多个集成电路芯片的三维模块。 IC芯片以多个基板的方式安装。平行于每行是提供信号路径的通信条，允许一个基板上的芯片与另一个基板上的芯片通信。通信条也用作衬底之间的间隔物，从而形成冷却通道。 IC芯片设置在冷却通道中，使得它们与冷却流体直接接触。来往于IC芯片的信号线保持尽可能与电源线分开，以使噪声最小化。为此，相对较厚的电源带安装到每行IC芯片下方的每个基板。电源带又连接到馈电带，使得保持到IC芯片的非常低的阻抗电源路径。本发明的三维结构的总体设计是高度模块化的，以便于高产量的制造和修理。

16. 发明授权

US5603892A System for maintaining a controlled atmosphere in an electronic circuit package 失效
标题翻译：用于在电子电路封装中维持受控气氛的系统
公开(公告)号：US5603892A
公开(公告)日：1997-02-18
申请号：US257068
申请日：1994-06-09
申请人： Carlo Grilletto , David A. Horine
发明人： Carlo Grilletto , David A. Horine
IPC分类号： H01L23/26 , H05K7/20 , G05B13/00 , A62B7/08 , G05B15/00 , G05D16/00
CPC分类号： H05K7/20381 , Y10S438/909
摘要： A system for maintaining electronic components, such as integrated circuit chips, in a contaminant-free controlled atmosphere is disclosed. The components, which may be mounted on a multichip module, are housed in a sealed enclosure and a positive pressure of contaminant-free gas, such as pure nitrogen, is maintained within the enclosure. A source of pressurized gas, controllably connected to the enclosure is provided and, preferably, an exhaust valve is used to equalize the pressure in the enclosure when it is necessary to access the interior for purposes of maintenance or repair. Preferably, there is a control system which monitors and maintains the proper level of pressure within the enclosure and which may be used to periodically flush the enclosure. Also preferably, one or more canisters of getter material are attached to the enclosure for removing contaminants.
摘要翻译：公开了一种用于将电子元件（例如集成电路芯片）维持在无污染物的受控气氛中的系统。可以安装在多芯片模块上的组件容纳在密封的外壳中，并且在外壳内保持无污染的气体（例如纯氮）的正压力。提供可控制地连接到外壳的加压气体源，并且优选地，当为了维护或修理而需要进入内部时，排气阀用于使外壳中的压力相等。优选地，存在一个控制系统，该控制系统监控和维持外壳内的适当水平的压力，并可用于周期性地冲洗外壳。还优选地，一个或多个吸气剂材料罐附接到外壳以除去污染物。

17. 发明授权

US5515604A Methods for making high-density/long-via laminated connectors 失效
标题翻译：制造高密度/长通孔层压连接器的方法
公开(公告)号：US5515604A
公开(公告)日：1996-05-14
申请号：US134374
申请日：1993-10-12
申请人： David A. Horine , David G. Love
发明人： David A. Horine , David G. Love
IPC分类号： H01R12/04 , H01R11/01 , H01R12/06 , H05K3/36
CPC分类号： H01R12/52 , H01R12/57 , Y10T29/49126 , Y10T29/49155 , Y10T29/49224
摘要： A high-density laminated connector having a plurality of rigid dielectric layers laminated together is described. The rigid construction of the connector permits precise dimensions of the connector and, thus, accurate attachment of adjacent interconnect substrates. The dielectric layers include traces which have contact pads or bumps formed at the surfaces of the connector for connection to the traces of one or more adjacent interconnect substrates. The contact pads may comprise soft gold, solder, or various elastomeric materials. The use of soft gold contacts enables the connector to be easily removed from an adjacent interconnect substrate. In other embodiments, the rigid dielectric layers may comprise recesses where the contact pads are placed. This ensures physical alignment of the interconnect substrate and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction. Thus, right-angle interconnections can be made. Cross-traces can be placed on each individual layer of dielectric and vias made through the dielectric layers to interconnect traces. The trace width can be economically and accurately narrowed to produce high aspect ratios and thus provide high signal density.
摘要翻译：描述了具有层叠在一起的多个刚性介电层的高密度层叠连接器。连接器的刚性结构允许连接器的精确尺寸，从而准确地附接相邻的互连基板。电介质层包括具有形成在连接器表面处的接触焊盘或凸点的迹线，用于连接到一个或多个相邻互连基板的迹线。接触垫可以包括软金，焊料或各种弹性体材料。使用软金触点使连接器能够容易地从相邻的互连基板移除。在其他实施例中，刚性电介质层可以包括其中放置接触垫的凹部。这确保互连基板和连接器的物理对准，使得当对连接器施加压力时维持尺寸完整性。连接器内的迹线可以具有不同的宽度，间距和方向。因此，可以进行直角互连。交叉迹线可以放置在通过介电层制成的介电层和通孔的每个单独层上以互连迹线。迹线宽度可以经济地和精确地缩小以产生高纵横比，从而提供高信号密度。

18. 发明授权

US5426563A Three-dimensional multichip module 失效
标题翻译：三维多芯片模块
公开(公告)号：US5426563A
公开(公告)日：1995-06-20
申请号：US157332
申请日：1993-11-22
申请人： Larry L. Moresco , David A. Horine , Wen-Chou V. Wang
发明人： Larry L. Moresco , David A. Horine , Wen-Chou V. Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H05K7/20
CPC分类号： H01L23/4985 , H01L21/486 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/3011 , Y10T29/49126
摘要： A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained. The overall design of the three dimensional structure of the present invention is highly modular to facilitate high yield fabrication and repair.
摘要翻译：示出了用于容纳多个集成电路芯片的三维模块。 IC芯片以多个基板的方式安装。平行于每行是提供信号路径的通信条，允许一个基板上的芯片与另一个基板上的芯片通信。通信条也用作衬底之间的间隔物，从而形成冷却通道。 IC芯片设置在冷却通道中，使得它们与冷却流体直接接触。来往于IC芯片的信号线保持尽可能与电源线分开，以使噪声最小化。为此，相对较厚的电源带安装到每行IC芯片下方的每个基板。电源带又连接到馈电带，使得保持到IC芯片的非常低的阻抗电源路径。本发明的三维结构的总体设计是高度模块化的，以便于高产量的制造和修理。

19. 发明授权

US6019814A Method of manufacturing 3D parts using a sacrificial material 失效
标题翻译：使用牺牲材料制造3D零件的方法
公开(公告)号：US6019814A
公开(公告)日：2000-02-01
申请号：US977813
申请日：1997-11-25
申请人： David A. Horine
发明人： David A. Horine
IPC分类号： C23C4/12 , B05D1/33 , B05D3/06
CPC分类号： C23C4/123
摘要： A method for manufacturing precise complex three dimensional structures in which minute drops of both a product layer and a sacrificial layer are emitted from an acoustic device. The process is a two step process wherein first the three dimensional structure is built in layers which are composed of either a sacrificial layer or a product layer or some configuration of both. Once the structure has been completely built up, then the sacrificial layer is removed leaving only the complex three dimensional structure.
摘要翻译：一种用于制造精密复杂三维结构的方法，其中从声学装置发射产物层和牺牲层的微滴。该过程是两步法，其中首先将三维结构内置在由牺牲层或产物层或两者的一些构型组成的层中。一旦完成了结构的构造，就消除牺牲层，只剩下复杂的三维结构。

20. 发明授权

US5930890A Structure and fabrication procedure for a stable post 失效
标题翻译：稳定桩的结构和制造程序
公开(公告)号：US5930890A
公开(公告)日：1999-08-03
申请号：US858192
申请日：1997-04-21
申请人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
IPC分类号： G03F7/26 , H01L21/48 , H01L23/12 , H01L23/52 , H05K3/18 , H05K3/40 , H01K3/10
CPC分类号： H05K3/4007 , H01L21/4853 , H01L2924/00013 , H05K2201/0347 , H05K2201/0367 , H05K2203/0577 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.
摘要翻译：通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱，宽孔径面罩或简单的UV空白洪水曝光。在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。然后可以通过电镀填充该开口以产生强大的整体互连柱。

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