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11. 发明申请

US20100187610A1 SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE 有权
标题翻译：具有双金属门的半导体器件及其制造方法
公开(公告)号：US20100187610A1
公开(公告)日：2010-07-29
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

12. 发明授权

US08450169B2 Replacement metal gate structures providing independent control on work function and gate leakage current 失效
标题翻译：替代金属栅极结构提供对功函数和栅极漏电流的独立控制
公开(公告)号：US08450169B2
公开(公告)日：2013-05-28
申请号：US12954946
申请日：2010-11-29
申请人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的阻挡金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

13. 发明申请

US20120132998A1 Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current 失效
标题翻译：替代金属栅极结构提供工作功能和栅极泄漏电流的独立控制
公开(公告)号：US20120132998A1
公开(公告)日：2012-05-31
申请号：US12954946
申请日：2010-11-29
申请人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

14. 发明授权

US08759172B2 Etch stop layer formation in metal gate process 失效
标题翻译：在金属栅极工艺中形成蚀刻停止层
公开(公告)号：US08759172B2
公开(公告)日：2014-06-24
申请号：US13449433
申请日：2012-04-18
申请人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
发明人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02164 , H01L21/02208 , H01L21/0228 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/66545
摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。栅极电介质盖形成在金属栅极导体上。栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

15. 发明申请

US20130277764A1 Etch Stop Layer Formation In Metal Gate Process 失效
标题翻译：金属浇口工艺中的蚀刻停止层形成
公开(公告)号：US20130277764A1
公开(公告)日：2013-10-24
申请号：US13449433
申请日：2012-04-18
申请人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
发明人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02164 , H01L21/02208 , H01L21/0228 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/66545
摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。栅极电介质盖形成在金属栅极导体上。栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

16. 发明授权

US08901706B2 Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches 有权
标题翻译：高稳定性高K四方HFO2层在高深宽比深沟内
公开(公告)号：US08901706B2
公开(公告)日：2014-12-02
申请号：US13345290
申请日：2012-01-06
申请人： Michael P. Chudzik , Bachir Dirahoui , Rishikesh Krishnan , Siddarth A. Krishnan , Oh-jung Kwon , Paul C. Parries , Hongwen Yan
发明人： Michael P. Chudzik , Bachir Dirahoui , Rishikesh Krishnan , Siddarth A. Krishnan , Oh-jung Kwon , Paul C. Parries , Hongwen Yan
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L21/02181 , H01L21/0228 , H01L21/02321 , H01L21/84 , H01L27/10847 , H01L27/1087 , H01L27/1203 , H01L29/945
摘要： A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
摘要翻译：在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。％至20重量％％。

17. 发明授权

US08643115B2 Structure and method of Tinv scaling for high κ metal gate technology 失效
标题翻译：用于高kappa金属栅极技术的Tinv缩放的结构和方法
公开(公告)号：US08643115B2
公开(公告)日：2014-02-04
申请号：US13006642
申请日：2011-01-14
申请人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
发明人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
IPC分类号： H01L27/092
CPC分类号： H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.
摘要翻译：提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个原子％N2和位于其中的pFET阈值电压调节物质。

18. 发明申请

US20130175665A1 THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES 有权
公开(公告)号：US20130175665A1
公开(公告)日：2013-07-11
申请号：US13345290
申请日：2012-01-06
申请人： Michael P. Chudzik , Bachir Dirahoui , Rishikesh Krishnan , Siddarth A. Krishnan , Oh-jung Kwon , Paul C. Parries , Hongwen Yan
发明人： Michael P. Chudzik , Bachir Dirahoui , Rishikesh Krishnan , Siddarth A. Krishnan , Oh-jung Kwon , Paul C. Parries , Hongwen Yan
IPC分类号： H01L29/92 , H01L21/02 , H01L29/06 , H01L21/31
CPC分类号： H01L28/91 , H01L21/02181 , H01L21/0228 , H01L21/02321 , H01L21/84 , H01L27/10847 , H01L27/1087 , H01L27/1203 , H01L29/945
摘要： A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

19. 发明申请

US20130126986A1 GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES 有权
标题翻译：氧化锗无机原子层沉积硅氧化物和高K栅介质用于CMOS器件的包含通道的锗
公开(公告)号：US20130126986A1
公开(公告)日：2013-05-23
申请号：US13300146
申请日：2011-11-18
申请人： MaryJane Brodsky , Murshed M. Chowdhury , Michael P. Chudzik , Min Dai , Siddarth A. Krishnan , Shreesh Narasimha , Shahab Siddiqui
发明人： MaryJane Brodsky , Murshed M. Chowdhury , Michael P. Chudzik , Min Dai , Siddarth A. Krishnan , Shreesh Narasimha , Shahab Siddiqui
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/518 , H01L21/28255 , H01L27/0922 , H01L29/51 , H01L29/513 , H01L29/66575 , H01L29/78
摘要： A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.
摘要翻译：一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体与高k栅介质层接触。氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。源极区域和漏极区域可以存在于沟道区域的相对侧上。

20. 发明申请

US20130105879A1 NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
标题翻译：使用高K门电介质和金属门的非易失性存储器结构
公开(公告)号：US20130105879A1
公开(公告)日：2013-05-02
申请号：US13326767
申请日：2011-12-15
申请人： Nicolas Breil , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon
发明人： Nicolas Breil , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28273 , H01L21/0228 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/11546 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/7881
摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
摘要翻译：用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和用于非易失性随机存取存储器（NVRAM）器件的高k隧道电介质）同时形成在半导体衬底上。随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。沉积并图案化平坦化介电层，并且去除一次性材料部分。控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

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