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11. 发明授权

US06697888B1 Buffering and interleaving data transfer between a chipset and memory modules 有权
标题翻译：在芯片组和存储器模块之间缓冲和交织数据传输
公开(公告)号：US06697888B1
公开(公告)日：2004-02-24
申请号：US09675304
申请日：2000-09-29
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F300
CPC分类号： G06F13/4234
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。这些缓冲区允许将存储器接口拆分成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织缓冲器的输出，以及配置缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

12. 发明授权

US06493250B2 Multi-tier point-to-point buffered memory interface 有权
标题翻译：多层点对点缓冲存储器接口
公开(公告)号：US06493250B2
公开(公告)日：2002-12-10
申请号：US09753024
申请日：2000-12-28
申请人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G11C506
CPC分类号： G06F13/4256
摘要： Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.
摘要翻译：公开了使用分支点对点存储器总线架构的存储器系统的方法和装置。在一个实施例中，主存储器控制器维护与一个存储器模块的点对点总线连接，并且该存储器模块与第二模块维护单独的点到点总线连接。存储器控制器和第二存储器模块之间的数据通过第一存储器模块上的缓冲电路。对于从存储器控制器接收到的数据，缓冲电路还将该数据上传到模块总线段到第一组存储器件。该存储器组存储有第二组存储器件的第二模块总线段。在缓冲电路和第二组存储器件之间的数据通过在第一存储器件组上通过一个通过电路。以这种方式，即使当存储器模块包含多于一组的存储器设备时，也可以维持点对点存储器总线体系结构。

13. 发明授权

US5797020A Bus master arbitration circuitry having improved prioritization 失效
公开(公告)号：US5797020A
公开(公告)日：1998-08-18
申请号：US692207
申请日：1996-08-05
申请人： Randy M. Bonella , Maria L. Melo
发明人： Randy M. Bonella , Maria L. Melo
IPC分类号： G06F13/362 , G06F13/364 , G06F13/14
CPC分类号： G06F13/364
摘要： An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

14. 发明授权

US5537555A Fully pipelined and highly concurrent memory controller 失效
标题翻译：完全流水线和高度并发的内存控制器
公开(公告)号：US5537555A
公开(公告)日：1996-07-16
申请号：US34290
申请日：1993-03-22
申请人： John A. Landry , Gary W. Thome , Paul A. Santeler , Randy M. Bonella , Michael J. Collins
发明人： John A. Landry , Gary W. Thome , Paul A. Santeler , Randy M. Bonella , Michael J. Collins
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G06F13/00
CPC分类号： G06F13/1615
摘要： A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
摘要翻译：一个内存控制器，最大程度地利用任何处理器流水线并同时运行大量的周期。存储器控制器可以利用不同的速度存储器件并以其期望的最佳速度运行每个存储器件。这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。当每个状态机完成其功能时，它通知相关的状态机它现在可以继续，并继续等待下一个启动或继续指示。下一台状态机以类似的方式运行。负责循环早期部分的状态机在下一个循环中开始执行任务，然后负责循环后期部分的状态机完成任务。存储器控制器在逻辑上组织为三个主要块，前端块，存储器块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。存储器控制器使用不同的速度存储器件，例如60ns和80ns，各个存储器件以其完全设计的速率工作。存储器的速度存储每个128 KB的存储器块，并且当发生存储器周期以重定向状态机时使用，实现存储器件的定时改变。

15. 发明授权

US5253358A Cache memory expansion and transparent interconnection 失效
标题翻译：缓存内存扩展和透明互连
公开(公告)号：US5253358A
公开(公告)日：1993-10-12
申请号：US883049
申请日：1992-05-07
申请人： Roy E. Thoma, III , Joseph P. Miller , Bill Skelton , Mark Taylor , Randy M. Bonella
发明人： Roy E. Thoma, III , Joseph P. Miller , Bill Skelton , Mark Taylor , Randy M. Bonella
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0886
摘要： A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.
摘要翻译：通过32位数据总线复用64位宽的存储器，以将数据提供给由82385缓存控制器控制的64位行大小的高速缓冲存储器。在整个传输期间，保存所有64位存储器的存储器地址，从而发生零等待状态第二次32位传输。逻辑开发所需的下一个地址和就绪脉冲，并从缓存控制器阻止这些信号。逻辑还处理主和高速缓冲存储器的位2地址。主存储器以分页模式运行，以进一步提高系统性能。

16. 发明授权

US06820163B1 Buffering data transfer between a chipset and memory modules 有权
标题翻译：缓冲芯片组和内存模块之间的数据传输
公开(公告)号：US06820163B1
公开(公告)日：2004-11-16
申请号：US09666489
申请日：2000-09-18
申请人： James A. McCall , Randy M. Bonella , John B. Halbert , Jim M. Dodd , Chung Lam
发明人： James A. McCall , Randy M. Bonella , John B. Halbert , Jim M. Dodd , Chung Lam
IPC分类号： G06F1300
CPC分类号： G11C7/1006 , G06F13/4256
摘要： Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器模块之间缓冲数据传输。本公开包括提供和配置至少一个缓冲器。缓冲器提供在芯片组和存储器模块之间的接口中。缓冲区允许将接口拆分为第一和第二子接口。第一子接口在芯片组和至少一个缓冲器之间。第二子接口位于至少一个缓冲器和存储器模块之间。然后将缓冲器配置为适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

17. 发明授权

US06742098B1 Dual-port buffer-to-memory interface 有权
标题翻译：双端口缓冲存储器接口
公开(公告)号：US06742098B1
公开(公告)日：2004-05-25
申请号：US09678751
申请日：2000-10-03
申请人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F1200
CPC分类号： G06F13/4256
摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.
摘要翻译：公开了使用新的存储器模块结构的存储器系统的方法和装置。在一个实施例中，存储器模块具有两个等级的存储器件，每个等级连接到两个64位宽数据寄存器中对应的一个。数据寄存器连接到120：64多路复用器/解复用器的两个64位宽端口，64位宽数据缓冲器连接到多路复用器/解复用器的相对端口。控制器同步数据寄存器，多路复用器/解复用器和数据缓冲器的操作。在操作环境中，数据缓冲器连接到存储器总线。当执行数据访问时，在单个数据访问期间，两者都与其对应的数据寄存器交换数据信令。在缓冲器中，存储器总线数据传输发生在两个连续的时钟周期中，每个等级都有一个周期。这允许存储器总线传输速率对于相同的存储器总线宽度和存储器件速度来说是双倍的。

18. 发明授权

US06530006B1 System and method for providing reliable transmission in a buffered memory system 有权
标题翻译：用于在缓冲存储器系统中提供可靠传输的系统和方法
公开(公告)号：US06530006B1
公开(公告)日：2003-03-04
申请号：US09664982
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams , John Halbert , Randy M. Bonella
发明人： James M. Dodd , Michael W. Williams , John Halbert , Randy M. Bonella
IPC分类号： G06F1200
CPC分类号： G06F13/4239
摘要： The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.
摘要翻译：本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。该系统包括存储器件，存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。缓冲器互连存储器件和存储器控制器。时钟电路嵌入到addr / cmd缓冲区中。时钟电路接收输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟偏移。

19. 发明授权

US06487102B1 Memory module having buffer for isolating stacked memory devices 无效
标题翻译：具有用于隔离堆叠存储器件的缓冲器的存储器模块
公开(公告)号：US06487102B1
公开(公告)日：2002-11-26
申请号：US09666528
申请日：2000-09-18
申请人： John B. Halbert , Randy M. Bonella
发明人： John B. Halbert , Randy M. Bonella
IPC分类号： G11C502
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04
摘要： The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.
摘要翻译：本发明利用缓冲器来隔离存储器件堆叠，从而利用可堆叠的存储器件可用的增加的存储器密度，同时降低容性负载。根据本发明的存储器模块可以包括堆叠的存储器件和缓冲器，其耦合到第一和第二存储器件并被布置成将第一和第二存储器件与总线电容隔离。在根据本发明的存储器系统中，存储器件的多个缓冲堆栈优选地以点对点布置耦合，从而进一步减小电容负载。

20. 发明授权

US06449213B1 Memory interface having source-synchronous command/address signaling 有权
标题翻译：具有源同步命令/地址信令的存储器接口
公开(公告)号：US06449213B1
公开(公告)日：2002-09-10
申请号：US09664192
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella
发明人： James M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C5/063 , G11C7/1087 , G11C8/00 , G11C8/06
摘要： A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.
摘要翻译：存储器接口方案通过利用源同步信令将地址/命令信息发送到存储器件来减少传播延迟。根据本发明的存储器模块可以包括地址/命令缓冲器，其响应于地址/命令选通信号对地址/命令信息进行采样，然后将地址/命令信息传递到模块上的存储器件。可以使用重新定时电路来控制来自模块上的存储器件的读取数据的定时。

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