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11. 发明授权

US07680232B2 Method and apparatus for multi-mode clock data recovery 失效
标题翻译：多模时钟数据恢复的方法和装置
公开(公告)号：US07680232B2
公开(公告)日：2010-03-16
申请号：US11040342
申请日：2005-01-21
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim T Hoang
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim T Hoang
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
摘要翻译：所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。（CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

12. 发明授权

US07590174B2 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US07590174B2
公开(公告)日：2009-09-15
申请号：US11312181
申请日：2005-12-20
申请人： Wilson Wong , Rakesh H Patel , Sergey Shumarayev , Tin H Lai
发明人： Wilson Wong , Rakesh H Patel , Sergey Shumarayev , Tin H Lai
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

13. 发明授权

US07304494B2 Methods and apparatus to DC couple LVDS driver to CML levels 有权
标题翻译：将LVDS驱动程序直接耦合到CML级别的方法和设备
公开(公告)号：US07304494B2
公开(公告)日：2007-12-04
申请号：US11098832
申请日：2005-04-04
申请人： Wilson Wong , Tim T Hoang , Sergey Y Shumarayev , Rakesh H Patel , Simardeep Maangat
发明人： Wilson Wong , Tim T Hoang , Sergey Y Shumarayev , Rakesh H Patel , Simardeep Maangat
IPC分类号： H03K17/16
CPC分类号： H03K19/017545
摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.
摘要翻译：为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。此外，电阻下拉可以是可编程的。这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

14. 发明授权

US07812659B1 Clock signal circuitry for multi-channel data signaling 有权
标题翻译：用于多通道数据信号的时钟信号电路
公开(公告)号：US07812659B1
公开(公告)日：2010-10-12
申请号：US11432420
申请日：2006-05-10
申请人： Sergey Shumarayev , Rakesh H Patel , William W Bereza , Tim Tri Hoang , Thungoc Tran
发明人： Sergey Shumarayev , Rakesh H Patel , William W Bereza , Tim Tri Hoang , Thungoc Tran
IPC分类号： G06F1/04 , H04L7/00
CPC分类号： H03L7/22 , G06F1/06
摘要： A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.
摘要翻译：可编程逻辑器件（“PLD”）等具有多个数据发送器通道。某些电路由通道共享。共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。主要和全局辅助信号被分配到信道。每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

15. 发明授权

US07804892B1 Circuitry for providing programmable decision feedback equalization 有权
标题翻译：提供可编程判决反馈均衡的电路
公开(公告)号：US07804892B1
公开(公告)日：2010-09-28
申请号：US11347527
申请日：2006-02-03
申请人： Sergey Y Shumarayev , Rakesh H Patel
发明人： Sergey Y Shumarayev , Rakesh H Patel
IPC分类号： H03H7/40
CPC分类号： H04L25/03885 , H04L25/03057
摘要： Equalization circuitry may be implemented by cascading a plurality of equalization stages. Each equalization stage may compensate for some of the attenuation of a received data signal. Each equalization stage may also be configured to perform decision feedback equalization to remove distortion from the current bit of data signal caused by one of the preceding bits in the data signal. Each equalization stage may be controlled by a DFE coefficient that determines the amount of voltage with which to adjust the output of the equalization stage. The equalization circuitry may be implemented on a receiver that includes clock data recovery circuitry and a pipeline/deserializer for providing preceding bit values to the equalization stages.
摘要翻译：均衡电路可以通过级联多个均衡级来实现。每个均衡级可以补偿接收到的数据信号的一些衰减。每个均衡级还可以被配置为执行判决反馈均衡以从数据信号中的前一位之一引起的数据信号的当前位中去除失真。每个均衡级可以由DFE系数来控制，该DFE系数确定用于调整均衡级的输出的电压量。均衡电路可以在包括时钟数据恢复电路和流水线/解串器的接收机上实现，用于向均衡级提供先前的位值。

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