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11. 发明申请

US20050116037A1 Label identification system and coding method suited therefor 失效
标题翻译：标签识别系统及其编码方法
公开(公告)号：US20050116037A1
公开(公告)日：2005-06-02
申请号：US10504376
申请日：2003-02-12
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G06K19/07 , G06K7/08 , G06K17/00 , G06K19/067 , G09F3/00 , H04B5/02
CPC分类号： G06K7/10336 , G06K7/086 , G06K19/067
摘要： The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.
摘要翻译：本发明涉及一种标签识别系统，包括发送接收单元和识别标签，识别信息以数字识别信息字的形式存储在其上。使用聚合物技术预制的电路装置形式的识别标签上的电路的提供，并且随后通过导体迹线的胶印印刷识别信息，能够提供涉及在廉价大规模生产中能量消耗最小化。识别信息处理的大部分被传送到发送 - 接收单元。

12. 发明申请

US20080259665A1 Rectifier Circuit, Circuit Arrangement and Method for Manufactiring a Rectifier Circuit 审中-公开
标题翻译：整流电路，电路布置及整流电路制造方法
公开(公告)号：US20080259665A1
公开(公告)日：2008-10-23
申请号：US11629941
申请日：2005-05-18
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： H02M7/217
CPC分类号： H02M7/217 , G01S13/75 , H02M7/219
摘要： One aspect of the invention relates to a rectifier circuit for providing a rectified voltage, with a first AC voltage terminal to which an AC voltage can be applied, with a first DC voltage terminal to which a DC voltage can be provided, and with a control switching element between the first AC voltage terminal and the first DC voltage terminal. The control switching element only couples the first AC voltage terminal to the first DC voltage terminal if the electrical potential at the first AC voltage terminal has a predeterminable polarity compared with a reference potential and if the amount of the electrical potential at the first DC voltage terminal is less than or equal to the amount of the electrical potential at the first AC voltage terminal.
摘要翻译：本发明的一个方面涉及一种用于提供整流电压的整流器电路，其中可以施加有交流电压的第一交流电压端子与可以提供直流电压的第一直流电压端子和控制器第一交流电压端子和第一直流电压端子之间的开关元件。如果第一AC电压端子的电位与参考电位相比具有可预定的极性，并且如果第一直流电压端子处的电位量，则控制开关元件仅将第一AC电压端子耦合到第一DC电压端子小于或等于第一AC电压端子处的电位量。

13. 发明申请

US20070279120A1 Noise-Reducing Transistor Arrangement, Integrated Circuit, and Method for Reducing the Noise of Field Effect Transistors 有权
标题翻译：降噪晶体管布置，集成电路和降低场效应晶体管噪声的方法
公开(公告)号：US20070279120A1
公开(公告)日：2007-12-06
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/16
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

14. 发明授权

US07817037B2 Electronic component with ID tags 有权
标题翻译：具有ID标签的电子元件
公开(公告)号：US07817037B2
公开(公告)日：2010-10-19
申请号：US10562458
申请日：2004-06-30
申请人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G08B13/14 , H03K7/08
CPC分类号： G06K19/0723
摘要： The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.
摘要翻译：本发明涉及可以通过交流电压操作的电子部件。所述组件包括具有相同功能的至少一个输入，至少一个输出和一对电子子部件。电子部件的输入端以相同的功能耦合到电子子部件的相应输入端，并且电子部件的输出耦合到所述电子部件的相应输出端，组件。此外，电子部件被配置为使得在交流电压的第一半波期间可以拾取一对功能相同的电子部件中的第一子部件的至少一个输出信号的一个输出信号，而一对功能相同的电子对的第二子分量的一个输出信号可以在交流电压的第二个半波期间被拾取。

15. 发明授权

US07342421B2 CMOS circuit arrangement 有权
标题翻译： CMOS电路布置
公开(公告)号：US07342421B2
公开(公告)日：2008-03-11
申请号：US10573362
申请日：2004-09-17
申请人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
发明人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/01728 , H01L2924/0002 , H03K19/0963 , H01L2924/00
摘要： In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit. At least a portion of the NMOS field effect transistors of the NMOS logic circuit have a first threshold voltage and at least a portion of the PMOS field effect transistors of the PMOS logic circuit have a third threshold voltage. The first clock transistor has a second threshold voltage. The first threshold voltage is lower than the second threshold voltage.
摘要翻译：在本发明的实施例中，提供了一种CMOS电路装置。 CMOS电路装置包括提供具有PMOS场效应晶体管的逻辑功能的PMOS逻辑电路，其中第一工作电位被馈送到PMOS逻辑电路的输入，提供逻辑功能的NMOS逻辑电路，具有NMOS场效应晶体管，第一时钟晶体管，其第一源极/漏极端子耦合到NMOS逻辑电路的输入，其中时钟信号被施加到第一时钟晶体管的栅极端子，并且其中第二工作电位被馈送到第二源极/漏极端子。 PMOS逻辑电路的输出和NMOS逻辑电路的输出彼此耦合。此外，逆变器电路耦合到PMOS逻辑电路的输出端和NMOS逻辑电路的输出。 NMOS逻辑电路的NMOS场效应晶体管的至少一部分具有第一阈值电压，PMOS逻辑电路的PMOS场效应晶体管的至少一部分具有第三阈值电压。第一时钟晶体管具有第二阈值电压。第一阈值电压低于第二阈值电压。

16. 发明授权

US07429001B2 Label identification system and coding method suited therefor 失效
标题翻译：标签识别系统及其编码方法
公开(公告)号：US07429001B2
公开(公告)日：2008-09-30
申请号：US10504376
申请日：2003-02-12
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G06K19/06 , G06K7/08 , H04Q5/22
CPC分类号： G06K7/10336 , G06K7/086 , G06K19/067
摘要： The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.
摘要翻译：本发明涉及一种标签识别系统，包括发送接收单元和识别标签，识别信息以数字识别信息字的形式存储在其上。使用聚合物技术预制的电路装置形式的识别标签上的电路的提供，并且随后通过导体迹线的胶印印刷识别信息，能够提供涉及在廉价大规模生产中能量消耗最小化。识别信息处理的大部分被传送到发送 - 接收单元。

17. 发明申请

US20070085582A1 ELECTRONIC COMPONENT WITH ID TAGS 有权
标题翻译：具有ID标签的电子组件
公开(公告)号：US20070085582A1
公开(公告)日：2007-04-19
申请号：US10562458
申请日：2004-06-30
申请人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： H03K7/08
CPC分类号： G06K19/0723
摘要： The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.
摘要翻译：本发明涉及可以通过交流电压操作的电子部件。所述组件包括具有相同功能的至少一个输入，至少一个输出和一对电子子部件。电子部件的输入端以相同的功能耦合到电子子部件的相应输入端，并且电子部件的输出耦合到所述电子部件的相应输出端，组件。此外，电子部件被配置为使得在交流电压的第一半波期间可以拾取一对功能相同的电子部件中的第一子部件的至少一个输出信号的一个输出信号，而一对功能相同的电子对的第二子分量的一个输出信号可以在交流电压的第二个半波期间被拾取。

18. 发明申请

US20070085567A1 Cmos circuit arrangement 有权
标题翻译： Cmos电路布置
公开(公告)号：US20070085567A1
公开(公告)日：2007-04-19
申请号：US10573362
申请日：2004-09-17
申请人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
发明人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
IPC分类号： H03K19/0175
CPC分类号： H03K19/01728 , H01L2924/0002 , H03K19/0963 , H01L2924/00
摘要： A clock transistor and a second operating potential functioning as a circuit breaker, are mounted between the outlet of an NMOS logic circuit.
摘要翻译：用作断路器的时钟晶体管和第二工作电位安装在NMOS逻辑电路的出口之间。

19. 发明申请

US20110013668A1 SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开
标题翻译：半导体电路布置及相关的温度检测方法
公开(公告)号：US20110013668A1
公开(公告)日：2011-01-20
申请号：US12888528
申请日：2010-09-23
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
IPC分类号： G01K7/01 , H01L29/74 , H01L27/06
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译：公开了半导体电路装置和温度检测方法。一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极实现场效应晶体管。在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层边区。

20. 发明申请

US20090101975A1 Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor 有权
标题翻译：包括场效应晶体管，特别是隧道场效应晶体管的集成电路布置
公开(公告)号：US20090101975A1
公开(公告)日：2009-04-23
申请号：US11816822
申请日：2005-12-09
申请人： Juergen Holz , Ronald Kakoschke , Thomas Nirschl , Christian Pacha , Klaus Schruefer , Thomas Schulz , Doris Schmitt-Landsiedel
发明人： Juergen Holz , Ronald Kakoschke , Thomas Nirschl , Christian Pacha , Klaus Schruefer , Thomas Schulz , Doris Schmitt-Landsiedel
IPC分类号： H01L29/02
CPC分类号： H01L27/0886 , H01L21/823418 , H01L21/823462 , H01L27/1052 , H01L27/1203 , H01L29/66795 , H01L29/7391 , H01L29/7392 , H01L29/78 , H01L29/785 , H01L29/7854 , H01L29/7856
摘要： An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.
摘要翻译：具体地说，具有与同一集成电路装置（10）上的其它晶体管（T2）相比具有较厚栅极电介质（GD1）的隧道场效应晶体管的解释。作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域（D1，S1）之间的界面。

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