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11. 发明授权

US07525179B2 Lead frame structure with aperture or groove for flip chip in a leaded molded package 失效
标题翻译：引线框架结构，带引线模制封装中的倒装芯片的孔或凹槽
公开(公告)号：US07525179B2
公开(公告)日：2009-04-28
申请号：US11448962
申请日：2006-06-06
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/495 , H01L23/28
CPC分类号： H01L24/40 , H01L21/565 , H01L23/49503 , H01L23/49548 , H01L23/49562 , H01L24/37 , H01L24/81 , H01L2224/16 , H01L2224/16245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/81801 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/37099
摘要： A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.
摘要翻译：公开了一种半导体管芯封装。在一个实施例中，管芯封装包括包括第一表面和第二表面的半导体管芯，以及具有管芯附着区域的引线框架结构以及远离管芯附着区域延伸的多个引线。管芯附着区域包括一个或多个孔。成型材料围绕引线框架结构的芯片附接区域和半导体管芯的至少一部分。成型材料也在一个或多个孔内。

12. 发明申请

US20090032300A1 Method of and apparatus for providing an RF shield on an electronic component 有权
标题翻译：在电子部件上提供RF屏蔽的方法和装置
公开(公告)号：US20090032300A1
公开(公告)日：2009-02-05
申请号：US12221256
申请日：2008-07-31
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H05K9/00 , B05D5/12 , C23C14/34
CPC分类号： H05K9/0024 , H05K1/0218 , H05K3/284 , H05K3/4015 , H05K2201/10242 , H05K2203/041 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146
摘要： A shielding assembly is configured to provide electromagnetic shielding and environmental protection to one or more electronic components coupled to a substrate. The shielding assembly includes a non-conductive mold compound layer, such as a dielectric epoxy. The mold compound layer is applied to a top surface of the substrate, thereby covering the electronic components and providing protection against environmentally induced conditions such as corrosion, humidity, and mechanical stress. The shielding assembly also includes a conductive layer applied to a top surface of the mold compound layer. The conductive layer is coupled to a ground plane in the substrate, thereby enabling the electromagnetic shielding function. The conductive layer is coupled to the ground plane via one or more metallized contacts that are coupled to the substrate and extend through the mold compound layer.
摘要翻译：屏蔽组件被配置为向耦合到衬底的一个或多个电子部件提供电磁屏蔽和环境保护。屏蔽组件包括非导电模制化合物层，例如电介质环氧树脂。模具化合物层被施加到基板的顶表面，从而覆盖电子部件并且提供防止诸如腐蚀，湿度和机械应力的环境诱发条件的保护。屏蔽组件还包括施加到模具化合物层的顶表面的导电层。导电层耦合到衬底中的接地平面，从而实现电磁屏蔽功能。导电层通过一个或多个金属化触点耦合到接地平面，金属化触点耦合到衬底并延伸穿过模具化合物层。

13. 发明申请

US20070249092A1 Semiconductor die package including multiple dies and a common node structure 有权
标题翻译：半导体管芯封装包括多个管芯和一个共同的节点结构
公开(公告)号：US20070249092A1
公开(公告)日：2007-10-25
申请号：US11410504
申请日：2006-04-24
申请人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
发明人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
IPC分类号： H01L21/00
CPC分类号： H01L23/49575 , H01L23/492 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.
摘要翻译：公开了一种能够安装在母板上的半导体管芯封装。半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

14. 发明申请

US20070132091A1 Thermal enhanced upper and dual heat sink exposed molded leadless package 失效
标题翻译：热增强型上，下两个散热片裸露无铅封装
公开(公告)号：US20070132091A1
公开(公告)日：2007-06-14
申请号：US11299270
申请日：2005-12-09
申请人： Chung-Lin Wu , Rajeev Joshi
发明人： Chung-Lin Wu , Rajeev Joshi
IPC分类号： H01L23/34
CPC分类号： H01L21/561 , H01L21/4828 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68377 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
摘要翻译：半导体封装包括半导体器件30和模制的上部散热片10。散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。环形平面基座11围绕升高或突出的中心区域12。该区域由基座11的平面支撑在四个倾斜壁13.1-13.4之上。壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。围绕环形基座11的外周围是四个支撑臂18.1-18.4。支撑臂相对于平面环形基座11的内表面16以钝角设置。

15. 发明授权

US07196313B2 Surface mount multi-channel optocoupler 有权
标题翻译：表面贴装多通道光电耦合器
公开(公告)号：US07196313B2
公开(公告)日：2007-03-27
申请号：US10817195
申请日：2004-04-02
申请人： Maria Clemens Y. Quinones , Rajeev Joshi
发明人： Maria Clemens Y. Quinones , Rajeev Joshi
IPC分类号： H01L31/00 , G02B27/00
CPC分类号： G02B6/4201 , H01L2224/48091 , H01L2224/48247 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： An optocoupler package is disclosed. The optocoupler package includes a substrate comprising a leadframe and a molding compound, and a plurality of optocouplers, each optocoupler including (i) an optical emitter, (ii) an optical receiver, (iii) and an optically transmissive medium disposed between the optical emitter and optical receiver, where the optical emitter and the optical receiver are electrically coupled to the leadframe.
摘要翻译：公开了一种光耦合器封装。光耦合器包括包括引线框架和模制化合物的基板和多个光耦合器，每个光耦合器包括（i）光发射器，（ii）光接收器，（iii）和设置在光发射器和光接收器，其中光发射器和光接收器电耦合到引线框架。

16. 发明授权

US07101734B2 Flip chip substrate design 有权
公开(公告)号：US07101734B2
公开(公告)日：2006-09-05
申请号：US10660866
申请日：2003-09-11
申请人： Honorio T. Granada , Rajeev Joshi , Connie Tangpuz
发明人： Honorio T. Granada , Rajeev Joshi , Connie Tangpuz
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/041 , H01L23/3107 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/00014 , H01L2224/13099
摘要： A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.

17. 发明授权

US07029947B2 Flip chip in leaded molded package with two dies 有权
公开(公告)号：US07029947B2
公开(公告)日：2006-04-18
申请号：US10834752
申请日：2004-04-28
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/12 , H01L23/3157 , H01L23/49562 , H01L23/49575 , H01L24/11 , H01L24/16 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13099 , H01L2224/16 , H01L2224/16245 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/18161 , H01L2924/30107 , H01L2924/00 , H01L2224/05644 , H01L2924/00014 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166
摘要： A chip device including two stacked dies. The chip device includes a leadframe that includes a plurality of leads. A first die is coupled to a first side of the leadframe with solder and a second die is coupled to a second side of the leadframe with solder. A molded body surrounds at least a portion of the leadframe and the dies.

18. 发明授权

US07008868B2 Passivation scheme for bumped wafers 失效
公开(公告)号：US07008868B2
公开(公告)日：2006-03-07
申请号：US10818647
申请日：2004-04-05
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/14 , H01L2224/03831 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/1403 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2224/05647 , H01L2924/00014 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166
摘要： A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

19. 发明申请

US20050275089A1 Package and method for packaging an integrated circuit die 审中-公开
标题翻译：用于封装集成电路管芯的封装和方法
公开(公告)号：US20050275089A1
公开(公告)日：2005-12-15
申请号：US10864909
申请日：2004-06-09
申请人： Rajeev Joshi , Maria Estacio , David Chong , B. H. Gooi , Stephen Martin
发明人： Rajeev Joshi , Maria Estacio , David Chong , B. H. Gooi , Stephen Martin
IPC分类号： H01L21/48 , H01L23/24 , H01L23/31 , H01L23/34 , H01L23/433 , H01L23/495
CPC分类号： H01L23/4334 , H01L23/3107 , H01L23/49548 , H01L23/49551 , H01L24/29 , H01L24/48 , H01L2224/05599 , H01L2224/05647 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/83805 , H01L2224/85051 , H01L2224/85399 , H01L2224/85986 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/351 , H01L2224/85186 , H01L2924/00 , H01L2224/45099 , H01L2224/48227 , H01L2924/3512 , H01L2924/00012 , H01L2224/4554
摘要： An integrated circuit assembly includes a lead frame having a plurality of leads with inner portions. A thermally-conductive clip member is bonded to the inner portions of the leads such that the clip member is electrically isolated from and yet thermally coupled to the lead frame. An integrated circuit die is bonded and thereby thermally coupled to the clip member. The die is electrically connected to the wire die by wire bonds. Encapsulant material is disposed over the inner portions of the leads and at least a portion of the clip member, and encapsulates the die and the wire bonds.
摘要翻译：集成电路组件包括具有多个具有内部部分的引线的引线框架。导热夹构件结合到引线的内部，使得夹构件与引线框架电隔离并且热耦合到引线框架。集成电路芯片被结合，从而热耦合到夹子构件。模具通过引线键与导线管芯电连接。封装材料设置在引线的内部部分和夹子构件的至少一部分上，并封装模具和引线接合。

20. 发明授权

US06836023B2 Structure of integrated trace of chip package 失效
标题翻译：芯片封装集成轨迹的结构
公开(公告)号：US06836023B2
公开(公告)日：2004-12-28
申请号：US10413796
申请日：2003-04-14
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/492 , H01L24/13 , H01L24/37 , H01L24/40 , H01L2224/05124 , H01L2224/05569 , H01L2224/05573 , H01L2224/05666 , H01L2224/05684 , H01L2224/13 , H01L2224/13099 , H01L2224/37147 , H01L2224/40225 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.
摘要翻译：公开了一种半导体管芯封装。管芯封装包括具有第一侧和第二侧的半导体管芯，垂直晶体管和第一侧的接合焊盘。具有第一孔的钝化层位于第一侧上，并且接合焊盘通过第一孔露出。底涂层冶金层与钝化层直接接触。底部基底冶金层位于第一孔内并与接合垫接触。包含第二孔的电介质层处于与底涂层冶金层直接接触的位置。焊料结构位于底涂层冶金层上，并且位于介电层的第二孔内。

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