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11. 发明申请

WO2021041952A1 MEMORY WITH DYNAMIC VOLTAGE SCALING 审中-公开
公开(公告)号：WO2021041952A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/048593
申请日：2020-08-28
申请人： QUALCOMM INCORPORATED
发明人： SUH, Jungwon , LO, Michael Hawjing , CHUN, Dexter Tamio , LELOUP, Xavier Loic , MOLL, Laurent Rene
IPC分类号： G06F1/324 , G06F1/3234 , G06F1/3296 , G11C5/14
摘要： Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

12. 发明申请

WO2020180677A1 ENHANCED DATA CLOCK OPERATIONS IN MEMORY 审中-公开
公开(公告)号：WO2020180677A1
公开(公告)日：2020-09-10
申请号：PCT/US2020/020374
申请日：2020-02-28
申请人： QUALCOMM INCORPORATED
发明人： SUH, Jungwon , CHUN, Dexter Tamio , LO, Michael Hawjing , THOZIYOOR, Shyamkumar , KUMAR, Ravindra
IPC分类号： G11C7/10 , G06F1/3237 , G06F1/3234
摘要： Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

13. 发明申请

WO2019040183A1 DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开
公开(公告)号：WO2019040183A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/039978
申请日：2018-06-28
申请人： QUALCOMM INCORPORATED
发明人： SUH, Jungwon , ARTIERI, Alain , CHUN, Dexter Tamio , SRIRAMAGIRI, Deepti Vijayalakshmi
IPC分类号： G06F11/10
摘要： Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

14. 发明申请

WO2018200132A1 OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION 审中-公开
公开(公告)号：WO2018200132A1
公开(公告)日：2018-11-01
申请号：PCT/US2018/025690
申请日：2018-04-02
申请人： QUALCOMM INCORPORATED
发明人： ARTIERI, Alain , SRIRAMAGIRI, Deepti Vijayalakshmi , CHUN, Dexter Tamio , SUH, Jungwon
IPC分类号： H04L1/00 , H03M13/19
CPC分类号： G06F11/10 , G06F3/0619 , G06F3/064 , G06F3/0673 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/19 , H04L1/0041 , H04L1/0045 , H04L1/0057
摘要： Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M , and storing the first three-bit code in the matrix M .

15. 发明申请

WO2017172267A1 POWER-REDUCING MEMORY SUBSYSTEM HAVING A SYSTEM CACHE AND LOCAL RESOURCE MANAGEMENT 审中-公开
标题翻译：降低功耗的内存子系统具有系统高速缓存和本地资源管理
公开(公告)号：WO2017172267A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020810
申请日：2017-03-03
申请人： QUALCOMM INCORPORATED
发明人： LI, Yanru , CHUN, Dexter Tamio , ARTIERI, Alain
IPC分类号： G06F13/16 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3275 , G06F12/0862 , G06F13/1689 , G06F2212/1021 , G06F2212/1024 , G06F2212/222 , G06F2212/602 , G11C11/40607 , G11C2211/4067 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.
摘要翻译：公开了用于降低存储器子系统功率的方法的系统，方法和计算机程序。在示例性方法中，系统资源管理器将多个存储器客户端的存储器性能要求提供给双倍数据速率（DDR）子系统。 DDR子系统和系统资源管理器驻留在电耦合到动态随机存取存储器（DRAM）的片上系统（SoC）上。与驻留在DDR子系统上的系统高速缓存相关联的多个存储器客户端中的每一个确定高速缓存命中率。 DDR子系统基于从系统资源管理器接收的存储器性能要求和多个存储器客户端的高速缓存命中率来控制DDR时钟频率。

16. 发明申请

WO2016089632A1 SYSTEMS AND METHODS FOR PROVIDING IMPROVED LATENCY IN A NON-UNIFORM MEMORY ARCHITECTURE 审中-公开
标题翻译：在非均匀存储器架构中提供改进的延迟的系统和方法
公开(公告)号：WO2016089632A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/061989
申请日：2015-11-20
申请人： QUALCOMM INCORPORATED
发明人： MOLLOY, Stephen Arthur , CHUN, Dexter Tamio
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1072 , G06F15/163 , G06F2212/1024 , G06F2212/2542 , G06F2212/657 , G11C7/1072
摘要： Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining whether a number of available physical pages on the first and second local volatile memory devices exceeds a minimum threshold for initiating replication of memory data between the first and second local volatile memory devices; and if the minimum threshold is exceeded, allocating a first physical address on the first local volatile memory device and a second physical address on the second local volatile memory device to a single virtual page address.
摘要翻译：公开了用于在具有非均匀存储器架构的便携式计算设备中分配存储器的系统，方法和计算机程序。一种方法的一个实施例包括：从在芯片上的第一系统（SoC）上执行对虚拟存储器页面的请求的处理，所述第一SoC经由芯片间接口电耦合到第二SoC，所述第一SoC电耦合到经由第一高性能总线的第一本地易失性存储器件，并且所述第二SoC经由第二高性能总线电耦合到第二本地易失性存储器件; 确定所述第一和第二本地易失性存储器设备上的可用物理页数是否超过用于在所述第一和第二本地易失性存储器设备之间启动存储器数据的复制的最小阈值; 并且如果超过所述最小阈值，则将所述第一本地易失性存储器设备上的第一物理地址和所述第二本地易失性存储器设备上的第二物理地址分配到单个虚拟页地址。

17. 发明申请

WO2016089631A1 SYSTEMS AND METHODS FOR PROVIDING IMPROVED LATENCY IN A NON-UNIFORM MEMORY ARCHITECTURE 审中-公开
标题翻译：在非均匀存储器架构中提供改进的延迟的系统和方法
公开(公告)号：WO2016089631A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/061987
申请日：2015-11-20
申请人： QUALCOMM INCORPORATED
发明人： MOLLOY, Stephen Arthur , CHUN, Dexter Tamio
IPC分类号： G06F12/10
CPC分类号： G06F12/023 , G06F12/0223 , G06F12/1072 , G06F15/163 , G06F2212/1024 , G06F2212/1044 , G06F2212/2542 , G11C7/1072 , G11C7/1075
摘要： Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining a free physical page pair comprising a same physical address available on the first and second local volatile memory devices; and mapping the free physical page pair to a single virtual page address.
摘要翻译：公开了用于在具有不均匀存储器架构的便携式计算设备中分配存储器的系统，方法和计算机程序。一种方法的一个实施例包括：从在第一片上系统（SoC）上执行对虚拟存储器页的请求的处理，所述第一SoC经由芯片间接口电耦合到第二SoC，所述第一SoC电耦合到第一本地易失性存储器设备经由第一高性能总线，并且所述第二SoC经由第二高性能总线电耦合到第二本地易失性存储器设备; 确定包括在所述第一和第二本地易失性存储器设备上可用的相同物理地址的空闲物理页对; 并将自由物理页对映射到单个虚拟页地址。

18. 发明申请

WO2016048628A1 DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS 审中-公开
标题翻译：动态随机存取时间调整
公开(公告)号：WO2016048628A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/048587
申请日：2015-09-04
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , DROP, Michael , SANKURATRI, Raghu
IPC分类号： G06F13/16
CPC分类号： G11C7/1072 , G06F13/1689
摘要： A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.
摘要翻译：一种方法包括在控制器处检测要发送到第一时间的动态随机存取存储器（DRAM）的第一数据业务和第二时间发送到DRAM的第二数据业务之间的变化率。该方法还包括响应于变化率满足阈值的确定来调整第二数据业务的数据速率。

19. 发明申请

WO2016028607A1 SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP 审中-公开
标题翻译：用于扩展芯片系统的存储器的系统和方法
公开(公告)号：WO2016028607A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/045133
申请日：2015-08-13
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , CHITTULURI, Suryanarayana China , LI, Yanru
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F3/0607 , G06F3/0631 , G06F3/0665 , G06F3/0683 , G06F12/0246 , G06F12/06 , G06F12/10 , G06F13/1684 , G06F2212/1048 , G06F2212/152 , G06F2212/171 , G06F2212/206 , G06F2212/214 , G06F2212/261 , G06F2212/654 , G06F2212/7201
摘要： Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.
摘要翻译：公开了用于扩展片上系统（SoC）的存储器的系统和方法。存储卡电气地装载在可扩展存储器插槽中，并通过扩展总线耦合到片上系统（SoC）。存储卡包括第一易失性存储器件。响应于检测到存储卡，配置扩展的虚拟存储器映射。扩展的虚拟存储器映射包括与第一易失性存储器设备相关联的第一虚拟存储器空间和与经由存储器总线电耦合到SoC的第二易失性存储器设备相关联的第二虚拟存储器空间。与第二虚拟存储器空间相关联的一个或多个周边图像被重新定位到第一虚拟存储器空间的第一部分。第一虚拟存储器空间的第二部分被配置为用于执行与第二虚拟存储器空间相关联的交换操作的块设备。

20. 发明申请

WO2015073900A1 METHOD AND APPARATUS FOR MULTIPLE-BIT DRAM ERROR RECOVERY 审中-公开
标题翻译：用于多位DRAM错误恢复的方法和装置
公开(公告)号：WO2015073900A1
公开(公告)日：2015-05-21
申请号：PCT/US2014/065809
申请日：2014-11-14
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , KIM, Jung Pill , SHIN, Hyunsuk , SUH, Jungwon
IPC分类号： G06F11/10 , G06F11/14
CPC分类号： G06F11/1072 , G06F11/1048 , G06F11/14 , G11C29/765
摘要： A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.
摘要翻译：当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且重新映射器被配置为使得将来对页面的访问被重定向到冗余页面。

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