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11. 发明申请

WO2023049620A1 RETURN-TO-ZERO (RZ) DIGIT AL-TO-ANALOG CONVERTER (DAC) FOR IMAGE CANCELLATION 审中-公开
公开(公告)号：WO2023049620A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/075860
申请日：2022-09-01
申请人： QUALCOMM INCORPORATED
发明人： MAHMOUDIDARYAN, Parisa , SAPUTRA, Nitz , SEO, Dongwon , MEHDIZAD TALEIE, Shahin
IPC分类号： H03M1/06 , H03M1/66
摘要： Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first retum-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

12. 发明申请

WO2023278923A1 DIGITAL AMPLITUDE TRACKING CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER 审中-公开
公开(公告)号：WO2023278923A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/072698
申请日：2022-06-01
申请人： QUALCOMM INCORPORATED
发明人： MEHDIZAD TALEIE, Shahin , SEO, Dongwon , SWAMINATHAN, Ashok , SAHOTA, Gurkanwal Singh , WEIL, Andrew , FEI, Haibo
IPC分类号： H03M1/74 , H03M1/12 , H03M1/78 , H03M1/002 , H03M1/1295 , H03M1/466 , H03M1/502 , H03M1/742 , H03M1/747 , H03M1/785
摘要： Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

13. 发明申请

WO2022094521A1 MISMATCH AND TIMING CORRECTION TECHNIQUE FOR MIXING-MODE DIGITAL-TO-ANALOG CONVERTER (DAC) 审中-公开
公开(公告)号：WO2022094521A1
公开(公告)日：2022-05-05
申请号：PCT/US2021/071838
申请日：2021-10-13
申请人： QUALCOMM INCORPORATED
发明人： LIU, Xilin , MAHMOUDIDARYAN, Parisa , MEHDIZAD TALEIE, Shahin , RASHIDI, Negar , SEO, Dongwon
IPC分类号： H03M1/10 , H03K5/05 , H03K5/156 , H03M1/66 , H03K5/00
摘要： Certain aspects of the present disclosure generally relate to circuitry and techniques for digital -to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

14. 发明申请

WO2016122836A1 SELF-SENSING REVERSE CURRENT PROTECTION SWITCH 审中-公开
标题翻译：自感式反向电流保护开关
公开(公告)号：WO2016122836A1
公开(公告)日：2016-08-04
申请号：PCT/US2016/012072
申请日：2016-01-04
申请人： QUALCOMM INCORPORATED
发明人： JI, Honghao , SEO, Dongwon
IPC分类号： H01L27/02 , H01L23/60 , H01L23/62 , H02H11/00 , H02H9/04
CPC分类号： H02H3/18 , H01L27/0266 , H01L27/0292 , H02H11/003
摘要： A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail.
摘要翻译：提供了一个反向电流保护（RCP）电路，其包括耦合在电源轨和缓冲电源节点之间的RCP开关。由缓冲器电源节点上的缓冲器电源供电的控制电路控制RCP开关响应于在电源轨上承载的电源电压的放电而打开。

15. 发明申请

WO2015183496A1 HYBRID R-2R STRUCTURE FOR LOW GLITCH NOISE SEGMENTED DAC 审中-公开
标题翻译：混合R-2R结构用于低玻璃噪声分离DAC
公开(公告)号：WO2015183496A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/029535
申请日：2015-05-06
申请人： QUALCOMM INCORPORATED
发明人： LEE, Sang Min , SEO, Dongwon
IPC分类号： H03M1/06 , H03M1/08 , H03M1/68 , H03M1/78
CPC分类号： H03M1/0863 , H03M1/0612 , H03M1/0881 , H03M1/687 , H03M1/785
摘要： The apparatus may be an N-bit DAC including (2M-1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M-1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.
摘要翻译：该装置可以是包括与M个最高有效位相关联的（2M-1）个并行级和与（N-M）个最低有效位相关联的（N-M）级的N位DAC。（2M-1）并联级可以将第一电流传送到DAC的电流求和节点。（N-M）级可以包括电阻网络和第二对开关，并且可以将第二电流传递到级的电阻网络。每个电阻网络可以根据对应于电阻网络的级的二进制权重来缩放分别传递的电流，并且可以将缩放的电流传送到一对电流求和节点。（N-M）级中的至少一个可以与其余级分离。

16. 发明公开

EP4238220A1 MISMATCH AND TIMING CORRECTION TECHNIQUE FOR MIXING-MODE DIGITAL-TO-ANALOG CONVERTER (DAC) 审中-实审
公开(公告)号：EP4238220A1
公开(公告)日：2023-09-06
申请号：EP21805816.2
申请日：2021-10-13
申请人： QUALCOMM INCORPORATED
发明人： LIU, Xilin , MAHMOUDIDARYAN, Parisa , MEHDIZAD TALEIE, Shahin , RASHIDI, Negar , SEO, Dongwon
IPC分类号： H03M1/10 , H03K5/05 , H03K5/156 , H03M1/66 , H03K5/00

17. 发明授权

EP3146628B1 DIFFERENTIAL MODE BANDWIDTH EXTENSION TECHNIQUE WITH COMMON MODE COMPENSATION 有权
公开(公告)号：EP3146628B1
公开(公告)日：2020-01-01
申请号：EP15727107.3
申请日：2015-05-07
申请人： Qualcomm Incorporated
发明人： KONG, Derui , LEE, Sang Min , MCGOWAN, Michael Joseph , SEO, Dongwon
IPC分类号： H03F1/14 , H03F3/45

18. 发明授权

EP2759107B1 LOAD DETECTING IMPEDANCE MATCHING BUFFER 有权
标题翻译：负载检测阻抗匹配缓冲器
公开(公告)号：EP2759107B1
公开(公告)日：2018-03-14
申请号：EP12780935.8
申请日：2012-09-24
申请人： Qualcomm Incorporated
发明人： CHIABURU, Liviu , TALEIE, Shahin Medhizah , SEO, Dongwon , SILVERSTEIN, Roy B.
IPC分类号： H04L25/02
CPC分类号： H04L25/0278
摘要： A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.

19. 发明公开

EP2965431A1 LOW GLITCH-NOISE DAC 有权
标题翻译： DAC MIT NIEDRIGEMSTÖRUNGSRAUSCHEN
公开(公告)号：EP2965431A1
公开(公告)日：2016-01-13
申请号：EP14713304.5
申请日：2014-03-04
申请人： Qualcomm Incorporated
发明人： SEO, Dongwon , LEE, Sang Min
IPC分类号： H03M1/08 , H03M1/68 , H03M1/74 , H03M1/78
CPC分类号： H03M1/785 , H03M1/0863 , H03M1/687 , H03M1/747
摘要： An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M−1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N−M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N−M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.
摘要翻译： N位数模转换器（DAC）包括N个输入级，每个输入级产生相同的电流量，并且包括响应于差分位的一对类似尺寸的晶体管开关。与DAC的M个最高有效位相关联的2M-1个输入级并联连接，并将其电流差分地传递给DAC的当前求和节点。剩余的（N-M）级中的每一个包括电阻网络，其提供由DAC内的级的位位置的二进制权重定义的电流。（N-M）级将电流差分地传递给当前求和节点。 DAC进一步包括阻抗衰减器，其适于在由设置在阻抗衰减器中的差分放大器的增益限定的范围内保持电流求和节点的阻抗和电流求和节点之间的电压差。

20. 发明授权

EP2269311B1 APPARATUS AND METHOD FOR DYNAMIC CIRCUIT ELEMENT SELECTION IN A DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：装置和方法的动态电路元件选择用在数字模拟转换器
公开(公告)号：EP2269311B1
公开(公告)日：2012-06-20
申请号：EP09762966.1
申请日：2009-03-08
申请人： QUALCOMM Incorporated
发明人： SEO, Dongwon , McALLISTER, Gene H. , DABAG, Hayg-Taniel
IPC分类号： H03M1/06 , H03M1/00
CPC分类号： H03M1/004 , H03M1/066 , H03M1/0665 , H03M1/0673 , H03M1/74 , H03M3/502
摘要： According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

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