专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

WO2016148927A1 CONDUCTIVE CAP FOR METAL-GATE TRANSISTOR 审中-公开
标题翻译：金属栅晶体导电帽
公开(公告)号：WO2016148927A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/020628
申请日：2016-03-03
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , SONG, Stanley Seungchul
IPC分类号： H01L29/49 , H01L29/51 , H01L21/28 , H01L29/423
CPC分类号： H01L29/4958 , H01L21/28079 , H01L21/28114 , H01L21/28247 , H01L21/32133 , H01L21/7684 , H01L21/76877 , H01L21/76897 , H01L21/823475 , H01L23/528 , H01L23/53238 , H01L29/0649 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66568 , H01L29/78
摘要： A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.
摘要翻译：半导体器件包括栅极区，导电帽和互连。栅极区域（例如，金属栅极晶体管）包括金属栅极区域和高介电常数（高K）栅极电介质区域。导电盖设置在金属栅极区域的表面上和高K栅极电介质区域的表面上，并且互连件设置在导电帽上。导电盖包括将栅极区域与互连电连接的导电材料。

12. 发明申请

WO2022217169A1 THREE DIMENSIONAL (3D) VERTICAL SPIRAL INDUCTOR AND TRANSFORMER 审中-公开
公开(公告)号：WO2022217169A1
公开(公告)日：2022-10-13
申请号：PCT/US2022/070566
申请日：2022-02-08
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , YANG, Bin , YANG, Haining
IPC分类号： H01F17/00 , H01F41/04 , H01F27/28 , H01L49/02
摘要： Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

13. 发明申请

WO2021022275A1 FINFET SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2021022275A1
公开(公告)日：2021-02-04
申请号：PCT/US2020/070089
申请日：2020-05-29
申请人： QUALCOMM INCORPORATED
发明人： YANG, Bin , YANG, Haining , LI, Xia
IPC分类号： H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12
摘要： A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

14. 发明申请

WO2020060703A1 CIRCUITS EMPLOYING A DOUBLE DIFFUSION BREAK (DDB) AND SINGLE DIFFUSION BREAK (SDB) IN DIFFERENT TYPE DIFFUSION REGIONS, AND RELATED FABRICATION METHODS 审中-公开
公开(公告)号：WO2020060703A1
公开(公告)日：2020-03-26
申请号：PCT/US2019/047013
申请日：2019-08-19
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , DENG, Jie
IPC分类号： H01L21/8238 , H01L27/02 , H01L29/78 , H01L27/118
摘要： Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P- type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N- type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

15. 发明申请

WO2017023910A1 FINFET DEVICE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译： FINFET器件及其制造方法
公开(公告)号：WO2017023910A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/045117
申请日：2016-08-02
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , LIU, Yanxiang
IPC分类号： H01L21/84 , H01L27/12 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/02164 , H01L21/26513 , H01L21/823821 , H01L21/823828 , H01L21/823892 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/66545 , H01L29/6681 , H01L29/7845
摘要： A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.
摘要翻译：根据这里的一些示例的finFET器件可以包括有源鳍元件上方的有源栅极元件和部分地断开有源栅极元件的虚设鳍元件。在另一示例中，与有源栅极元件相邻的伪栅极元件包含部分地断开伪栅极元件的虚设鳍元件。在另一个示例中，第一虚拟翅片元件部分地中断有源栅极元件，并且第二虚设鳍元件部分地断开伪栅极元件。在另一个示例中，虚拟翅片元件具有与活动翅片元件相同的材料。在另一个示例中，虚拟鳍片元件部分地打破栅极元件，但是不像活性鳍片元件那样延伸到衬底。

16. 发明申请

WO2016205409A1 HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY 审中-公开
标题翻译：混合色彩方法多图案技术
公开(公告)号：WO2016205409A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/037684
申请日：2016-06-15
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiangdong , LIM, Hyeokjin Bruce , KWON, Ohsang , MALABRY, Mickael , ZHANG, Jingwei , STEPHANY, Raymond George , YANG, Haining , RIM, Kern , SONG, Stanley Seungchul , GUPTA, Mukul , VANG, Foua
IPC分类号： G03F7/20 , G03F1/00 , G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5068
摘要： In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.
摘要翻译：在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

17. 发明申请

WO2016204938A1 SEMICONDUCTOR INTEGRATED CIRCUITS (ICs) EMPLOYING LOCALIZED LOW DIELECTRIC CONSTANT (LOW-K) MATERIAL IN INTER-LAYER DIELECTRIC (ILD) MATERIAL FOR IMPROVED SPEED PERFORMANCE 审中-公开
标题翻译：半导体集成电路（IC）采用局部低介电常数（低K）材料在层间介质（ILD）材料中改进速度性能
公开(公告)号：WO2016204938A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/033709
申请日：2016-05-23
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , CHEN, Xiangdong
IPC分类号： H01L23/532
CPC分类号： H01L29/0649 , H01L21/02282 , H01L21/762 , H01L21/768 , H01L23/5226 , H01L23/528 , H01L23/5329
摘要： Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.
摘要翻译：公开了在层间电介质（ILD）材料中采用局部低介电常数（低K）材料的半导体集成电路（IC），以提高速度性能。为了加快IC中所选择的电路的性能，否则会降低IC的整体速度性能，在IC制造过程中采用低K电介质材料。低K电介质材料设置在其中设置选择电路的ILD材料的选定的局部区域中。以这种方式，由于设置在低K ILD材料中的所选择的电路的电路元件和/或电路元件互连将经历减小的信号延迟，所以IC将在操作期间经历总体增加的速度性能。此外，通过仅在所选电路的ILD材料的选定的局部区域中使用低K电介质材料，机械和/或热稳定性涉及由于在所有ILD材料中使用低K电介质材料而引起的问题 IC被避免。

18. 发明申请

WO2016164447A1 FINFET WITH CUT GATE STRESSOR 审中-公开
标题翻译：具有切割闸门的FINFET
公开(公告)号：WO2016164447A1
公开(公告)日：2016-10-13
申请号：PCT/US2016/026195
申请日：2016-04-06
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , LIU, Yanxiang
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8238 , H01L21/84 , H01L27/092
CPC分类号： H01L29/7845 , H01L21/823431 , H01L21/823437 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/1037 , H01L29/4232 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.
摘要翻译：半导体鳍片包括沟道区域。由金属形成的闸应力部件横向于翅片延伸并且包括在通道区域中跨过翅片的门表面。闸门应力器构件具有包括与翅片间隔开切割距离的部分切割的构造。该结构通过栅极表面导致鳍中的横向应力，其具有对应于切割距离的大小。由金属形成的横向应力器构件在通道区域外的区域跨越翅片，并且在通道区域外的区域处引起翅片中额外的横向应力。对应于切割距离的大小与附加的横向应力相结合，在通道区域中引起纵向压缩应变。

19. 发明申请

WO2016154405A1 FINFET DEVICE FOR N/P TUNING 审中-公开
标题翻译：用于N / P调谐的FINFET器件
公开(公告)号：WO2016154405A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/023959
申请日：2016-03-24
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , YANG, Haining
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L27/0207 , H01L27/0924 , H01L27/1211 , H01L29/42356 , H01L29/66545 , H01L29/785 , H01L29/7851
摘要： The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.
摘要翻译：集成逻辑电路中的n型至p型鳍FET强度比可以通过在有源和虚拟栅电极中使用切割区来调节。在一些示例中，用于伪栅极电极和有源栅电极的单独的切割区域可以用于允许不同长度的栅极通过有源区域，从而导致适当调谐的集成逻辑电路。

20. 发明申请

WO2011097457A1 SYSTEMS AND METHODS FOR WRITING TO MULTIPLE PORT MEMORY CIRCUITS 审中-公开
标题翻译：用于写入多个端口存储器电路的系统和方法
公开(公告)号：WO2011097457A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023716
申请日：2011-02-04
申请人： QUALCOMM INCORPORATED , YANG, Haining , WANG, Zhongze , JUNG, ChangHo
发明人： YANG, Haining , WANG, Zhongze , JUNG, ChangHo
IPC分类号： G11C8/16 , G11C11/412
CPC分类号： G11C8/16 , G11C11/412
摘要： A multiple-port RAM circuit has a data-in line (DIN) coupled to multiple bit lines (a-bit, b-bit) and multiple bit line bars (a-bitb, b-bitb). The circuit also has multiple word lines (a-wl, b-wl). A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller (201) that enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.
摘要翻译：多端口RAM电路具有耦合到多个位线（a位，b位）和多位线条（a-bitb，b-bitb）的数据输入线（DIN）。该电路还具有多个字线（a-wl，b-wl）。存储器单元耦合到位线，位线条和字线。该电路还包括控制器（201），其使得字线能够基本上同时将来自位线的值写入存储器单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式