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11. 发明公开

EP3311405A1 STRUCTURE AND METHOD FOR TUNABLE MEMORY CELLS INCLUDING FIN FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：包括鳍场效应晶体管的可读存储器单元的结构和方法
公开(公告)号：EP3311405A1
公开(公告)日：2018-04-25
申请号：EP16730961.6
申请日：2016-06-06
申请人： Qualcomm Incorporated
发明人： YANG, Haining , LIU, Yanxiang
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L29/78 , H01L27/088 , H01L27/092 , H01L27/11 , H01L27/12
CPC分类号： H01L21/02 , G05B19/418 , G05B2219/45031 , H01L21/76895 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/785
摘要： In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

12. 发明申请

WO2021173243A1 COMPLEMENTARY CELL CIRCUITS EMPLOYING ISOLATION STRUCTURES FOR DEFECT REDUCTION AND RELATED METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2021173243A1
公开(公告)日：2021-09-02
申请号：PCT/US2021/013168
申请日：2021-01-13
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , BAO, Junjing
IPC分类号： H01L21/8238 , H01L27/092
摘要： To prevent short defects between source/d rains of transistors of a complementary cell circuit, isolation walls (414A) are formed in an isolation region between the source/d rains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type (412P) and N-type (412N) epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/d rain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls.

13. 发明申请

WO2021150392A1 GATE ALL AROUND TRANSISTORS WITH HIGH CHARGE MOBILITY CHANNEL MATERIALS 审中-公开
公开(公告)号：WO2021150392A1
公开(公告)日：2021-07-29
申请号：PCT/US2021/013004
申请日：2021-01-11
申请人： QUALCOMM INCORPORATED
发明人： YANG, Bin , YANG, Haining , LI, Xia
IPC分类号： H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L21/8252 , H01L21/823807 , H01L21/823878 , H01L27/0605 , H01L29/0673 , H01L29/1033 , H01L29/16 , H01L29/201 , H01L29/42392 , H01L29/432 , H01L29/66484 , H01L29/66522 , H01L29/7831 , H01L29/78696
摘要： A semiconductor device (200) comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor (206) and a P-type metal oxide semiconductor (PMOS) GAA transistor (222) with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate (202). The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material (210, 214). The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material (230, 234). The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.

14. 发明申请

WO2020112278A1 A STRUCTURE AND METHOD FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ISOLATION 审中-公开
公开(公告)号：WO2020112278A1
公开(公告)日：2020-06-04
申请号：PCT/US2019/057573
申请日：2019-10-23
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining
IPC分类号： H01L21/8234 , H01L21/8238 , H01L29/78
摘要： Aspects of the disclosure are directed to isolation in integrated circuits. In accordance with one aspect, implementing a complementary metal oxide semiconductor (CMOS) isolation in an integrated circuit (IC) includes etching an interlayer dielectric (ILD, 1425) between two of a plurality of gates in a first section (1401) of an integrated circuit (IC); etching a semiconductor substrate to form a trench within an active region in the first section; and filling the trench with an insulator (1419) in the first section and planarizing the integrated circuit (IC).

15. 发明申请

WO2018140195A1 SYSTEMS, METHODS, AND APPARATUS FOR IMPROVED FINFETS 审中-公开
公开(公告)号：WO2018140195A1
公开(公告)日：2018-08-02
申请号：PCT/US2018/012025
申请日：2018-01-02
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , YANG, Haining
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8234
摘要： To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

16. 发明申请

WO2017117225A1 SEMICONDUCTOR DEVICES WITH WIDER FIELD GATES FOR REDUCED GATE RESISTANCE 审中-公开
标题翻译：半导体器件具有更宽的栅极电阻，可降低栅极电阻
公开(公告)号：WO2017117225A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068883
申请日：2016-12-28
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , CHEN, Xiangdong
IPC分类号： H01L21/8234 , H01L29/423 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823437 , H01L27/0207 , H01L27/088 , H01L29/4238 , H01L29/66545 , H01L29/78
摘要： Semiconductor devices with wider field gates for reduced gate resistance are disclosed. In one aspect, a semiconductor device is provided that employs a gate. The gate is a conductive line disposed above the semiconductor device to form transistors corresponding to active semiconductor regions. Each active semiconductor region has a corresponding channel region. Portions of the gate disposed over each channel region are active gates, and portions not disposed over the channel region, but that are disposed over field oxide regions, are field gates. A voltage differential between each active gate and a source of each corresponding transistor causes current flow in a channel region when the voltage differential exceeds a threshold voltage. The width of each field gate is a larger width than each active gate. The larger width of the field gates results in reduced gate resistance compared to devices with narrower field gates.
摘要翻译：公开了具有用于降低栅极电阻的更宽场栅的半导体器件。在一个方面中，提供了一种采用栅极的半导体器件。栅极是设置在半导体器件上方的导电线，以形成对应于有源半导体区域的晶体管。每个有源半导体区域具有对应的沟道区域。布置在每个沟道区域上方的栅极的部分是有源栅极，并且未布置在沟道区域上方但布置在场氧化物区域上方的部分是场栅极。当电压差超过阈值电压时，每个有源栅极与每个对应晶体管的源极之间的电压差导致电流在沟道区中流动。每个场门的宽度比每个有源门的宽度大。与具有较窄场栅的器件相比，较大的场栅宽度导致栅极电阻降低。

17. 发明申请

WO2016148927A1 CONDUCTIVE CAP FOR METAL-GATE TRANSISTOR 审中-公开
标题翻译：金属栅晶体导电帽
公开(公告)号：WO2016148927A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/020628
申请日：2016-03-03
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , SONG, Stanley Seungchul
IPC分类号： H01L29/49 , H01L29/51 , H01L21/28 , H01L29/423
CPC分类号： H01L29/4958 , H01L21/28079 , H01L21/28114 , H01L21/28247 , H01L21/32133 , H01L21/7684 , H01L21/76877 , H01L21/76897 , H01L21/823475 , H01L23/528 , H01L23/53238 , H01L29/0649 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66568 , H01L29/78
摘要： A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.
摘要翻译：半导体器件包括栅极区，导电帽和互连。栅极区域（例如，金属栅极晶体管）包括金属栅极区域和高介电常数（高K）栅极电介质区域。导电盖设置在金属栅极区域的表面上和高K栅极电介质区域的表面上，并且互连件设置在导电帽上。导电盖包括将栅极区域与互连电连接的导电材料。

18. 发明申请

WO2022217169A1 THREE DIMENSIONAL (3D) VERTICAL SPIRAL INDUCTOR AND TRANSFORMER 审中-公开
公开(公告)号：WO2022217169A1
公开(公告)日：2022-10-13
申请号：PCT/US2022/070566
申请日：2022-02-08
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , YANG, Bin , YANG, Haining
IPC分类号： H01F17/00 , H01F41/04 , H01F27/28 , H01L49/02
摘要： Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

19. 发明申请

WO2021022275A1 FINFET SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2021022275A1
公开(公告)日：2021-02-04
申请号：PCT/US2020/070089
申请日：2020-05-29
申请人： QUALCOMM INCORPORATED
发明人： YANG, Bin , YANG, Haining , LI, Xia
IPC分类号： H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12
摘要： A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

20. 发明申请

WO2020060703A1 CIRCUITS EMPLOYING A DOUBLE DIFFUSION BREAK (DDB) AND SINGLE DIFFUSION BREAK (SDB) IN DIFFERENT TYPE DIFFUSION REGIONS, AND RELATED FABRICATION METHODS 审中-公开
公开(公告)号：WO2020060703A1
公开(公告)日：2020-03-26
申请号：PCT/US2019/047013
申请日：2019-08-19
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , DENG, Jie
IPC分类号： H01L21/8238 , H01L27/02 , H01L29/78 , H01L27/118
摘要： Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P- type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N- type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

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