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11. 发明授权

US06484230B1 Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction 失效
标题翻译：在完成前一同步指令之前推测加工指令的方法和系统
公开(公告)号：US06484230B1
公开(公告)日：2002-11-19
申请号：US09161640
申请日：1998-09-28
申请人： Brian R. Konigsburg , Alexander Edward Okpisz , Thomas Albert Petersen , Bruce Joseph Ronchetti
发明人： Brian R. Konigsburg , Alexander Edward Okpisz , Thomas Albert Petersen , Bruce Joseph Ronchetti
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： A method and system of facilitating storage accesses within a multiprocessor system subsequent to a synchronization instruction by a local processor consists of determining if data for the storage accesses is cacheable and if there is a “hit” in a cache. If both conditions are met, the storage accesses return the data to the local processor. The storage accesses have an entry on an interrupt table which is used to discard the returned data if a snoop kills the line before the synchronization instruction completes. After the cache returns data, a return data bit is set in the interrupt table. A snoop killing the line sets a snooped bit in the interrupt table. Upon completion of the synchronization instruction, any entries in the interrupt table subsequent to the synchronization instruction that have the return data bit and snooped bit set are flushed. The flush occurs because the data returned to the local processor due to a “cacheable hit” subsequent to the synchronization instruction was out of order with the snoop and the processor must flush the data and go back out to the system bus for the new data.
摘要翻译：在本地处理器的同步指令之后，便于在多处理器系统内存储访问的方法和系统包括确定用于存储访问的数据是否可高速缓存以及高速缓存中是否存在“命中”。如果满足这两个条件，存储访问将数据返回到本地处理器。存储访问在中断表上有一个条目，如果在同步指令完成之前窥探杀死了该行，则该条目用于丢弃返回的数据。缓存返回数据后，在中断表中设置返回数据位。一个窥探杀死线路在中断表中设置一个窥探的位。完成同步指令之后，刷新具有返回数据位和被监听位置位的同步指令之后的中断表中的任何条目。发生冲突是因为由于在同步指令之后的“可缓存命中”返回到本地处理器的数据与snoop不一致，并且处理器必须刷新数据并返回到系统总线以获取新数据。

12. 发明授权

US06301654B1 System and method for permitting out-of-order execution of load and store instructions 有权
标题翻译：允许无序执行加载和存储指令的系统和方法
公开(公告)号：US06301654B1
公开(公告)日：2001-10-09
申请号：US09213331
申请日：1998-12-16
申请人： Bruce Joseph Ronchetti , Dave Shippy , Larry Edward Thatcher
发明人： Bruce Joseph Ronchetti , Dave Shippy , Larry Edward Thatcher
IPC分类号： G06F738
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3842
摘要： In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. Then when new load or store instructions are issued, the new load or store instructions are compared to entries within the load and store reorder queues to detect out of order problems.
摘要翻译：在微处理器内的加载/存储单元中，加载和存储指令是无序执行的。加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。然后，当发出新的加载或存储指令时，将新的加载或存储指令与加载和存储重新排序队列中的条目进行比较，以检测出乱序问题。

13. 发明授权

US06237081B1 Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor 失效
标题翻译：排队方法和装置，用于便于在处理器中拒绝顺序指令
公开(公告)号：US06237081B1
公开(公告)日：2001-05-22
申请号：US09213319
申请日：1998-12-16
申请人： Hung Qui Le , Larry Edward Thatcher , Bruce Joseph Ronchetti , David James Shippy
发明人： Hung Qui Le , Larry Edward Thatcher , Bruce Joseph Ronchetti , David James Shippy
IPC分类号： G06F932
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.
摘要翻译：处理器（100）包括具有用于向执行单元（140）发出指令的发布队列（144）的发布单元（125）。执行单元（140）可接受并执行该指令或产生拒绝信号。在发出每条指令之后，发出队列（144）保留发出的关键周期指令。在关键时段之后，发布队列（144）可以放弃发出的指令，除非执行单元（140）已经产生了拒绝信号。如果执行单元（140）已经产生了拒绝信号，则指令最终在发布队列（144）中被标记为可重新发行。可以根据执行单元（140）的拒绝的性质来修改拒绝指令从重新发行保持的时间长度。此外，执行单元（140）可以响应于某些拒绝条件进行校正动作，使得可以在重新发布时完全执行该指令。

14. 发明授权

US07380062B2 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权
标题翻译：机制在多线程微处理器中维护最佳情况需求指令重新分配
公开(公告)号：US07380062B2
公开(公告)日：2008-05-27
申请号：US11055818
申请日：2005-02-11
申请人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译：一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。检查需求缺失的高速缓存行以确定关键部门。一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

15. 发明授权

US07350051B2 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream 有权
标题翻译：从页表条目优化有效页码到实际页码转换路径的方法匹配恢复执行流
公开(公告)号：US07350051B2
公开(公告)日：2008-03-25
申请号：US11054277
申请日：2005-02-09
申请人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
发明人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
IPC分类号： G06F12/10 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

16. 发明授权

US07284094B2 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权
标题翻译：允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中获取请求同时运行，而不管其一致等级
公开(公告)号：US07284094B2
公开(公告)日：2007-10-16
申请号：US11054293
申请日：2005-02-09
申请人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译：一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。确定这些识别的未完成的有效提取条目使用的SetID。所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。

17. 发明授权

US06490653B1 Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system 失效
标题翻译：用于根据数据处理系统中的推测性L2缓存命中来最优地发布依赖指令的方法和系统
公开(公告)号：US06490653B1
公开(公告)日：2002-12-03
申请号：US09325397
申请日：1999-06-03
申请人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1208
CPC分类号： G06F9/383 , G06F9/3842
摘要： A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.
摘要翻译：公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。处理系统包括主缓存和二级缓存。所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。该方法和系统包括确定第一指令是否在二级高速缓存内。所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成的周期。在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。问题队列使用信号在最佳时间发出相关指令。如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。

18. 发明授权

US06349382B1 System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order 失效
标题翻译：用于存储转发的系统为组分配负载和存储指令，并重新排序队列以跟踪程序顺序
公开(公告)号：US06349382B1
公开(公告)日：2002-02-19
申请号：US09263665
申请日：1999-03-05
申请人： Kurt Alan Feiste , Bruce Joseph Ronchetti , David James Shippy
发明人： Kurt Alan Feiste , Bruce Joseph Ronchetti , David James Shippy
IPC分类号： G06F1500
CPC分类号： G06F9/3834 , G06F9/3824
摘要： In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.
摘要翻译：在微处理器内的加载/存储单元中，加载和存储指令是无序执行的。加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。当执行加载指令时，确定加载指令是否试图将数据加载到与先前执行的存储指令正在等待完成的存储单元相同的存储单元。如果是这样，则通过存储指令等待存储在高速缓存内的数据被直接转发到加载指令。

19. 发明申请

US20080209177A1 Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch 有权
标题翻译：多线程微处理器中维护最佳案例需求指令重新分配的机制
公开(公告)号：US20080209177A1
公开(公告)日：2008-08-28
申请号：US12113561
申请日：2008-05-01
申请人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译：一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。检查需求缺失的高速缓存行以确定关键部门。一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

20. 发明授权

US07318127B2 Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权
标题翻译：用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品
公开(公告)号：US07318127B2
公开(公告)日：2008-01-08
申请号：US11055820
申请日：2005-02-11
申请人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/14
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译：在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。动态分配缓存以在多个线程之间使用。高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。在执行线程期间，可以动态地更改部分的大小。

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