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11. 发明授权

US07448014B2 Design stage mitigation of interconnect variability 有权
标题翻译：设计阶段缓解互连变异性
公开(公告)号：US07448014B2
公开(公告)日：2008-11-04
申请号：US11370538
申请日：2006-03-08
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

12. 发明授权

US08020134B2 Method and apparatus for parallel processing of semiconductor chip designs 有权
标题翻译：半导体芯片设计的并行处理方法和装置
公开(公告)号：US08020134B2
公开(公告)日：2011-09-13
申请号：US12035950
申请日：2008-02-22
申请人： Michael W. Dotson , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
发明人： Michael W. Dotson , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
摘要翻译：在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计使用一个或多个集群，并且并行设计各个分区。

13. 发明授权

US07930669B2 Stage mitigation of interconnect variability 有权
标题翻译：阶段缓解互连变异性
公开(公告)号：US07930669B2
公开(公告)日：2011-04-19
申请号：US12237246
申请日：2008-09-24
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

14. 发明授权

US07685553B2 System and method for global circuit routing incorporating estimation of critical area estimate metrics 失效
标题翻译：用于全局电路路由的系统和方法，其中包括关键面积估计度量的估计
公开(公告)号：US07685553B2
公开(公告)日：2010-03-23
申请号：US11733795
申请日：2007-04-11
申请人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
发明人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
摘要翻译：电子电路布局细化方法和系统。在电路布局区域上定义了一个大小相同的瓷砖网格。电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。执行用于放置在电网的多个瓦片内的电路的全局电路布线。在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。然后生成经调整的全局电路布线。

15. 发明授权

US5257201A Method to efficiently reduce the number of connections in a circuit 失效
标题翻译：有效减少电路中连接数量的方法
公开(公告)号：US5257201A
公开(公告)日：1993-10-26
申请号：US394247
申请日：1989-08-14
申请人： Charles L. Berman , Louise H. Trevillyan
发明人： Charles L. Berman , Louise H. Trevillyan
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/505
摘要： A provided logic circuitry implementation in a given technology includes n signals and m nodes. A final logic circuitry implementation is produced therefrom which is the functional equivalent of, and contains fewer connections than, the provided logic circuitry implementation. A given one of the n signals is first processed, and global information is computed for this signal. A graphical representation of connections between the m nodes is derived from the computed global information. A list of nodes that form a cut-set is produced from the graphical representation, and an optimized logic circuitry implementation is provided as a function thereof. Each of the remaining ones of the n signals are processed sequentially, as above, to form successive optimized logic circuitry implementations, with the processing of the nth signal resulting in the final logic circuitry implementation.
摘要翻译：在给定技术中提供的逻辑电路实现包括n个信号和m个节点。由此产生最终逻辑电路实现，其与所提供的逻辑电路实现的功能等同于并且包含更少的连接。首先对n个信号中的一个信号进行处理，并计算该信号的全局信息。从所计算的全局信息中导出m个节点之间的连接的图形表示。从图形表示产生形成剪切集的节点的列表，并且作为其功能提供优化的逻辑电路实现。如上所述，依次对n个信号中的剩余信号中的每一个进行处理，以形成连续优化的逻辑电路实现，第n个信号的处理产生最终的逻辑电路实现。

16. 发明申请

US20120159418A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES 有权
标题翻译：基于任务的多进程设计合成与变换签名的通知
公开(公告)号：US20120159418A1
公开(公告)日：2012-06-21
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

17. 发明申请

US20120159406A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS 有权
标题翻译：基于任务的多进程设计与可重构变换的合成
公开(公告)号：US20120159406A1
公开(公告)日：2012-06-21
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

18. 发明申请

US20080256502A1 SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS 失效
标题翻译：全球电路路由系统与方法，适用于关键领域估算的估计
公开(公告)号：US20080256502A1
公开(公告)日：2008-10-16
申请号：US11733795
申请日：2007-04-11
申请人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
发明人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
摘要翻译：电子电路布局细化方法和系统。在电路布局区域上定义了一个大小相同的瓷砖网格。电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。执行用于放置在电网的多个瓦片内的电路的全局电路布线。在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。然后生成经调整的全局电路布线。

19. 发明申请

US20130086537A1 Design Routability Using Multiplexer Structures 失效
标题翻译：使用多路复用器结构设计路由
公开(公告)号：US20130086537A1
公开(公告)日：2013-04-04
申请号：US13248119
申请日：2011-09-29
申请人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译：提供用于产生集成电路器件的逻辑设计的机构。接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

20. 发明授权

US08392866B2 Task-based multi-process design synthesis with notification of transform signatures 有权
标题翻译：基于任务的多进程设计综合与转换签名通知
公开(公告)号：US08392866B2
公开(公告)日：2013-03-05
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

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