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11. 发明授权

US06665765B1 Hot docking drive wedge and port replicator 失效
标题翻译：热对接驱动楔和端口复制器
公开(公告)号：US06665765B1
公开(公告)日：2003-12-16
申请号：US09515566
申请日：2000-02-29
申请人： Jeffrey C. Tang , Gregory N. Santos , Ronald P. Meyers, Jr.
发明人： Jeffrey C. Tang , Gregory N. Santos , Ronald P. Meyers, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： A portable computer can be “hot” docked to one or more expansion devices, such as a drive wedge and a port replicator. As such, the expansion devices can be connected to and disconnected from the portable computer while portable computer is powered on and fully operational. The portable computer includes control logic that detects when an expansion device is connected to or disconnected from the portable computer and asserts an SMI or equivalent interrupt signal to the computer's CPU to initiate a sequence of events by which the computer determines whether an expansion device has been connected or disconnected. If the CPU determines that the expansion device has been connected to the computer, the CPU appropriately reconfigures itself to communicate with the expansion device. If the expansion device is disconnected, the CPU also appropriately reconfigures itself to preclude communications with the disconnected device.
摘要翻译：便携式计算机可以“热”对接到一个或多个扩展设备，例如驱动楔和端口复制器。因此，当便携式计算机通电并且完全可操作时，扩展设备可以连接到便携式计算机并从便携式计算机断开。便携式计算机包括控制逻辑，其检测何时扩展设备连接到便携式计算机或与便携式计算机断开连接，并向计算机的CPU发出SMI或等效中断信号，以启动一系列事件，通过该事件顺序，计算机确定扩展设备是否已被连接或断开连接。如果CPU确定扩展设备已连接到计算机，则CPU适当地重新配置以与扩展设备通信。如果扩展设备断开连接，CPU也可以适当重新配置自己，以防止与断开连接的设备进行通信。

12. 发明授权

US5581714A Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus) 失效
标题翻译：总线读总线读取预取逻辑，用于改善多总线信息处理系统（用于优化系统总线和外围总线之间的数据传输的多总线信息处理系统的总线到总线桥）的信息传输
公开(公告)号：US5581714A
公开(公告)日：1996-12-03
申请号：US473659
申请日：1995-06-07
申请人： Nader Amini , Ashu Kohli , Gregory N. Santos
发明人： Nader Amini , Ashu Kohli , Gregory N. Santos
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/28
摘要： A method and system for improving bus-to-bus data transfers in a multi-bus computer system is provided. The system includes a system bus having a slave device attached thereto, a peripheral bus having a master device attached thereto, and a host bridge connecting the two buses. The system bus permits burst read transfers of data stored in the slave device, wherein a single address phase is followed by several data phases, but only if the first address corresponds to a prescribed system bus boundary. The peripheral bus is not subject to address boundary limitations, instead permitting burst read transfers beginning at any address. The host bridge includes logic for decoding a first address asserted by the master device to determine if it corresponds to a system bus boundary. If it does not, the logic commences a first read pre-fetch non-burst transfer of a first set of data stored in the slave device beginning at the first address and ending at a system bus boundary, and temporarily stores this first set of data in a buffer. The logic then commences a second read pre-fetch burst transfer of a second set of data stored in the slave device corresponding to data stored between system bus boundaries, and temporarily stores this second set of data in the buffer, so that both of the temporarily stored first and second sets of data may be read by the master device over the peripheral bus in a single burst read transfer.
摘要翻译：提供了一种用于在多总线计算机系统中改善总线到总线数据传输的方法和系统。该系统包括具有连接到其上的从设备的系统总线，连接有主设备的外围总线以及连接两条总线的主桥。系统总线允许对存储在从设备中的数据的突发读取传输，其中单个地址相位之后是几个数据相位，但是仅当第一地址对应于规定的系统总线边界时。外设总线不受地址边界限制，而是允许从任何地址开始的突发读取传输。主桥包括用于解码由主设备断言的第一地址以确定其是否对应于系统总线边界的逻辑。如果不存在，逻辑开始从第一地址开始存储在从设备中的第一组数据的第一次读取非突发传输，并以系统总线边界结束，并临时存储该第一组数据在缓冲区。然后逻辑开始对应于存储在系统总线边界之间的数据的存储在从设备中的第二组数据的第二读取预取突发传输，并将该第二组数据临时存储在缓冲器中，使得暂时存储的第一和第二组数据可以由主设备在单个突发读传输中通过外围总线读取。

13. 发明授权

US6040845A Device and method for reducing power consumption within an accelerated graphics port target 失效
标题翻译：用于降低加速图形端口目标内的功耗的装置和方法
公开(公告)号：US6040845A
公开(公告)日：2000-03-21
申请号：US995763
申请日：1997-12-22
申请人： Maria L. Melo , Gregory N. Santos
发明人： Maria L. Melo , Gregory N. Santos
IPC分类号： G06F1/32 , G06F13/364 , G06F13/14
CPC分类号： G06F1/3253 , G06F1/3203 , G06F13/364 , Y02B60/1235 , Y02B60/32
摘要： A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.
摘要翻译：提供一种计算机，其具有耦合在外围总线和专用图形总线之间的总线接口单元。图形总线可以通过AGP链接到总线接口单元，而外设总线可以通过PCI链接到总线接口单元。 AGP总线的仲裁可以确定何时授予AGP主控（即图形加速器/控制器）。在授予主管权之前，AGP目标将降低到总线接口单元内的功耗最小的低功耗状态。直到AGP主机达到掌握，总线接口单元内的图形目标（核心逻辑和存储器控制器）才能处于运行状态（完全供电）状态。因此，计算机采用总线接口单元，其可以根据对图形目标的访问而从高功率状态动态切换到低功率状态，反之亦然。

14. 发明授权

US5933158A Use of a link bit to fetch entries of a graphic address remapping table 失效
标题翻译：使用链接位来获取图形地址重映射表的条目
公开(公告)号：US5933158A
公开(公告)日：1999-08-03
申请号：US926426
申请日：1997-09-09
申请人： Gregory N. Santos , Robert C. Elliott
发明人： Gregory N. Santos , Robert C. Elliott
IPC分类号： G06F12/08 , G06F3/14 , G06F12/10 , G06F13/36 , G06T11/00 , G09G5/00 , G09G5/36 , G09G5/39 , G06F12/06
CPC分类号： G09G5/39 , G06F12/1027 , G06F12/1081 , G06F3/14 , G09G2360/121 , G09G2360/125 , G09G5/363
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向计算机系统物理存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联的图形数据页面的特征标志。其中一个特征标志被用作每个GART表条目的链接位，使得当核心逻辑芯片组读取存储在系统存储器中的GART表条目中的所选择的一个时，它将所选择的一个存储在其高速缓冲存储器中并确定其链路位是否被设置。如果所选择的第一个的链接位被设置，则所选择的一个的下一个被存储在高速缓冲存储器中，并且如果其链接位被设置，则所选择的一个的后续的一个被存储在高速缓冲存储器直到其中一个链接位被确定为不被设置。

15. 发明授权

US5914730A System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests 失效
标题翻译：用于加速和更新各个GART表条目以加速图形端口事务请求的系统和方法
公开(公告)号：US5914730A
公开(公告)日：1999-06-22
申请号：US926421
申请日：1997-09-09
申请人： Gregory N. Santos , Robert C. Elliott
发明人： Gregory N. Santos , Robert C. Elliott
IPC分类号： G06F12/08 , G06F3/14 , G06F12/10 , G06F13/36 , G06T11/00 , G09G5/00 , G09G5/36 , G09G5/39 , G06F13/16
CPC分类号： G06F3/14 , G06F12/1081 , G09G5/39 , G06F12/1027 , G09G2360/121 , G09G2360/125 , G09G5/363
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。 GART缓存条目控制寄存器由应用程序编程接口（如GART微型端口驱动程序）用于向核心逻辑芯片组指出芯片组缓存中的单个GART表条目应无效和/或更新。核心逻辑芯片组然后可以对单独的GART表条目执行所需的无效和/或更新操作，而不必刷新或以其它方式干扰存储在高速缓存中的其他仍然相关的GART表条目。

16. 发明授权

US06990546B2 Hot docking drive wedge and port replicator 失效
公开(公告)号：US06990546B2
公开(公告)日：2006-01-24
申请号：US10690905
申请日：2003-10-22
申请人： Jeffrey C. Tang , Gregory N. Santos , Ronald P. Meyers, Jr.
发明人： Jeffrey C. Tang , Gregory N. Santos , Ronald P. Meyers, Jr.
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： A portable computer can be “hot” docked to one or more expansion devices, such as a drive wedge and a port replicator. As such, the expansion devices can be connected to and disconnected from the portable computer while portable computer is powered on and fully operational. The portable computer includes control logic that detects when an expansion device is connected to or disconnected from the portable computer and asserts an SMI or equivalent interrupt signal to the computer's CPU to initiate a sequence of events by which the computer determines whether an expansion device has been connected or disconnected. If the CPU determines that the expansion device has been connected to the computer, the CPU appropriately reconfigures itself to communicate with the expansion device. If the expansion device is disconnected, the CPU also appropriately reconfigures itself to preclude communications with the disconnected device.

17. 发明授权

US5564026A Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system 失效
标题翻译：总线到总线起搏逻辑，用于改善多总线信息处理系统中的信息传输
公开(公告)号：US5564026A
公开(公告)日：1996-10-08
申请号：US477910
申请日：1995-06-07
申请人： Nader Amini , Ashu Kohli , Gregory N. Santos
发明人： Nader Amini , Ashu Kohli , Gregory N. Santos
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/28
摘要： Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.
摘要翻译：使用PCI总线架构或使用类似于PCI的总线架构的外设总线将系统总线连接到外设总线的主机桥内的硬件逻辑。硬件优化在总线之间完成数据传输的速度，同时在两条总线的不同架构之间转换数据传输。

18. 发明授权

US5550989A Bridge circuit that can eliminate invalid data during information transfer between buses of different bitwidths 失效
标题翻译：桥接电路可以在不同位宽的总线之间的信息传输过程中消除无效数据
公开(公告)号：US5550989A
公开(公告)日：1996-08-27
申请号：US69234
申请日：1993-05-28
申请人： Gregory N. Santos
发明人： Gregory N. Santos
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4018 , G06F13/28
摘要： Hardware logic within a host bridge that connects a CPU local bus to a peripheral bus that determines if data to be transmitted on the CPU local bus is non-contiguous and, if so, substitutes contiguous data for the non-contiguous data to ensure that the CPU local bus does not malfunction. Simultaneously, the hardware translates data transfers between a peripheral bus that is limited by its architecture to data strings of a standard length and a CPU local bus that permits dynamic bus sizing.
摘要翻译：将CPU本地总线连接到外围总线的主桥内的硬件逻辑，用于确定要在CPU本地总线上传输的数据是否不连续，如果是，则将连续的数据替换为不连续的数据，以确保 CPU本地总线不会发生故障。同时，硬件将受其架构限制的外围总线与标准长度的数据串和允许动态总线大小调整的CPU本地总线之间的数据传输进行转换。

19. 发明授权

US5864688A Apparatus and method for positively and subtractively decoding addresses on a bus 失效
标题翻译：用于对总线上的地址进行正负的解码的装置和方法
公开(公告)号：US5864688A
公开(公告)日：1999-01-26
申请号：US684584
申请日：1996-07-19
申请人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
发明人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
IPC分类号： G06F13/36 , G06F13/40 , G06F12/00
CPC分类号： G06F13/4045
摘要： A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.
摘要翻译：具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。该桥包括用于控制解码的内部设备和配置寄存器。用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。根据对接状态，由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

20. 发明授权

US5781748A Computer system utilizing two ISA busses coupled to a mezzanine bus 失效
标题翻译：利用耦合到夹层总线的两条ISA总线的计算机系统
公开(公告)号：US5781748A
公开(公告)日：1998-07-14
申请号：US671316
申请日：1996-07-19
申请人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
发明人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
IPC分类号： G06F13/40 , H01J13/00
CPC分类号： G06F13/4027
摘要： A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.
摘要翻译：具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。该桥包括用于控制解码的内部设备和配置寄存器。用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。根据对接状态，由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

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