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11. 发明申请

US20120098062A1 HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR 有权
标题翻译：混合有源场扩展漏磁MOS晶体管
公开(公告)号：US20120098062A1
公开(公告)日：2012-04-26
申请号：US13281260
申请日：2011-10-25
申请人： Sameer P. Pendharkar , John Lin
发明人： Sameer P. Pendharkar , John Lin
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/66681 , H01L29/0653 , H01L29/0696 , H01L29/0882 , H01L29/402 , H01L29/41758 , H01L29/4238 , H01L29/7816
摘要： An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.
摘要翻译：集成电路包括具有并行交替有源间隙漂移区和场间隙漂移区的扩展漏极MOS晶体管。扩展漏极MOS晶体管包括在场间隙漂移区域上具有场板的栅极。扩展漏极MOS晶体管可以形成为对称嵌套配置。用于形成包含延伸漏极MOS晶体管的集成电路的工艺提供并行的交替有源间隙漂移区域和场间隙漂移区域，栅极在场间隙漂移区域上具有场板。

12. 发明申请

US20090325352A1 METHODS OF FORMING DRAIN EXTENDED TRANSISTORS 有权
标题翻译：排水延伸晶体管的形成方法
公开(公告)号：US20090325352A1
公开(公告)日：2009-12-31
申请号：US12552471
申请日：2009-09-02
申请人： Sameer P. Pendharkar
发明人： Sameer P. Pendharkar
IPC分类号： H01L29/78 , H01L29/36
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1087 , H01L29/41 , H01L29/41725 , H01L29/42368 , H01L29/66659 , H03K19/00384
摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
摘要翻译：晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。在第一半导体区域和第二半导体区域之间存在界面。晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。还描述了一种混合技术电路。

13. 发明授权

US07414287B2 System and method for making a LDMOS device with electrostatic discharge protection 有权
标题翻译：制造具有静电放电保护功能的LDMOS器件的系统和方法
公开(公告)号：US07414287B2
公开(公告)日：2008-08-19
申请号：US11063312
申请日：2005-02-21
申请人： Sameer P. Pendharkar , Jonathan S. Brodsky
发明人： Sameer P. Pendharkar , Jonathan S. Brodsky
IPC分类号： H01L29/94
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

14. 发明授权

US06670685B2 Method of manufacturing and structure of semiconductor device with floating ring structure 有权
标题翻译：具有浮环结构的半导体器件的制造方法和结构
公开(公告)号：US06670685B2
公开(公告)日：2003-12-30
申请号：US10155543
申请日：2002-05-24
申请人： Sameer P. Pendharkar
发明人： Sameer P. Pendharkar
IPC分类号： H01L31119
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.
摘要翻译：高电压半导体器件包括设置在半导体衬底内的漏区。半导体器件还包括从半导体衬底的漏极区域向外设置的场氧化物层。半导体器件还包括从场氧化物层的至少一部分向内设置的浮动环结构。在一个具体实施例中，与半导体器件相关联的器件参数劣化包括在加速寿命操作大约五百（500）秒之后的一个百分之一或更少。

15. 发明授权

US6160290A Reduced surface field device having an extended field plate and method for forming the same 有权
公开(公告)号：US6160290A
公开(公告)日：2000-12-12
申请号：US196879
申请日：1998-11-20
申请人： Sameer P. Pendharkar , Taylor R. Efland
发明人： Sameer P. Pendharkar , Taylor R. Efland
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7813
摘要： A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at least one-half of the length of the field oxide layer (20).

16. 发明授权

US08598008B2 Stacked ESD clamp with reduced variation in clamp voltage 有权
标题翻译：堆叠的ESD钳位钳位电压变化较小
公开(公告)号：US08598008B2
公开(公告)日：2013-12-03
申请号：US13277939
申请日：2011-10-20
申请人： Sameer P. Pendharkar , Marie Denison , Yongxi Zhang
发明人： Sameer P. Pendharkar , Marie Denison , Yongxi Zhang
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L27/082 , H01L21/8222 , H01L27/0259 , H01L27/0823 , H01L29/735
摘要： An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
摘要翻译：公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。每个双极晶体管包括击穿诱导特征。击穿诱发特征相对于彼此具有反射对称性。还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。

17. 发明授权

US08154101B2 High voltage diode with reduced substrate injection 有权
公开(公告)号：US08154101B2
公开(公告)日：2012-04-10
申请号：US12537318
申请日：2009-08-07
申请人： Sameer P. Pendharkar , Binghua Hu
发明人： Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L29/861
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L27/0629 , H01L29/417 , H01L29/66136
摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

18. 发明授权

US06919603B2 Efficient protection structure for reverse pin-to-pin electrostatic discharge 有权
标题翻译：反向针对针静电放电的高效保护结构
公开(公告)号：US06919603B2
公开(公告)日：2005-07-19
申请号：US10426448
申请日：2003-04-30
申请人： Jonathan Brodsky , Robert Steinhoff , Sameer P. Pendharkar
发明人： Jonathan Brodsky , Robert Steinhoff , Sameer P. Pendharkar
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H03K19/003 , H01L23/62
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a first polarity, by a bipolar transistor (4C) formed in an n-well (64; 164), having a collector contact (72; 172) to one signal terminal (PIN1) and its emitter region (68; 168) and base (66; 166) connected to a second signal terminal (PIN2). For reverse polarity ESD protection, a diode (25) is formed in the same n-well (64; 164) by a p+ region (78; 178) connected to the second signal terminal (PIN2), serving as the anode. The cathode can correspond to the n-well (64; 164) itself, as contacted by the collector contact (72; 172). By using the same n-well (64; 164) for both devices, the integrated circuit chip area required to implement this pin-to-pin protection is much reduced.
摘要翻译：公开了一种用于防止信号端子之间的ESD事件的静电放电（ESD）保护结构。通过形成在n阱（64; 164）中的双极晶体管（4C）提供ESD保护，其具有到一个信号端子（PIN 1）的集电极触点（72; 172）及其发射极区域（68; 168）和连接到第二信号端子（PIN 2）的基座（66; 166）。对于反极性ESD保护，二极管（25）由连接到用作阳极的第二信号端子（PIN2）的p +区（78; 178）形成在同一个n阱（64; 164）中。阴极可以与收集器触点（72; 172）接触的n阱（64; 164）本身对应。通过对两个器件使用相同的n阱（64; 164），实现此引脚到引脚保护所需的集成电路芯片面积大大减少。

19. 发明授权

US06908859B2 Low leakage power transistor and method of forming 有权
标题翻译：低漏电功率晶体管及其形成方法
公开(公告)号：US06908859B2
公开(公告)日：2005-06-21
申请号：US10267264
申请日：2002-10-08
申请人： Sameer P. Pendharkar , Taylor R. Efland , William Nehrer
发明人： Sameer P. Pendharkar , Taylor R. Efland , William Nehrer
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/78 , H01L21/302
CPC分类号： H01L29/66659 , H01L21/823412 , H01L21/823493 , H01L29/1045 , H01L29/7835
摘要： A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.
摘要翻译：晶体管形成在半导体衬底中。深n井区域与浅的n阱区域结合使用。轻掺杂漏极延伸区域设置在漏极区域和栅极导体之间。区域的使用和区域的背景提供了非常高的击穿电压，与器件的相对低的沟道电阻相比。

20. 发明授权

US09362398B2 Low resistance LDMOS with reduced gate charge 有权
标题翻译：低电阻LDMOS具有减少的栅极电荷
公开(公告)号：US09362398B2
公开(公告)日：2016-06-07
申请号：US13281274
申请日：2011-10-25
申请人： Sameer P. Pendharkar
发明人： Sameer P. Pendharkar
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/402 , H01L29/4238 , H01L29/66659
摘要： An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap.
摘要翻译：一种集成电路，其包含具有与沟道区相邻的漏极漂移区域的MOS晶体管，漏极区域中的场氧化物元件，沟道区域上的第一栅极部分以及场氧化物元件上方的第二栅极部分之间的间隙，栅极部分，使得漂移区域的至少一半不被栅极覆盖。一种形成集成电路的过程，该集成电路包含具有与沟道区相邻的漏极漂移区的MOS晶体管，漏极区中的场氧化物元件，沟道区上的第一栅极部分和场氧化物元件上的第二栅极部分，在栅极部分之间具有间隙，使得至少一半的漂移区域不被栅极覆盖，使得源极/漏极注入被阻挡在间隙下方的漂移区域。

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