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11. 发明授权

US07705629B1 Permutable switching network with enhanced interconnectivity for multicasting signals 有权
标题翻译：具有增强的多播信号互联性的可互换交换网络
公开(公告)号：US07705629B1
公开(公告)日：2010-04-27
申请号：US12327702
申请日：2008-12-03
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H01L25/00
CPC分类号： H03K19/17736 , H01L21/768 , Y10T29/4913
摘要： In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
摘要翻译：在一个实施例中，集成电路具有包括L级中间导体的L电平可置换开关网络（L-PSN）。集成电路可用于电子设备，如交换网络，路由器和可编程逻辑电路等。

12. 发明授权

US07460529B2 Interconnection fabric using switching networks in hierarchy 有权
标题翻译：使用交换网络的互连结构在层次结构中
公开(公告)号：US07460529B2
公开(公告)日：2008-12-02
申请号：US10909810
申请日：2004-07-29
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H04Q11/00 , H03K19/00 , H03K19/173
CPC分类号： H04L49/15
摘要： An interconnection fabric using switching networks hierarchically to allow interconnections of large number of a first plurality of conductors to a large number of k plurality of conductors is described. The resulting interconnection fabric can be used in switching networks, routers and programmable logic circuits.
摘要翻译：描述了分层使用交换网络以允许大量第一多个导体与多个k个多个导体的互连的互连结构。所产生的互连结构可用于交换网络，路由器和可编程逻辑电路。

13. 发明申请

US20080272806A1 SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC 有权
标题翻译：可编程逻辑的可扩展非阻塞切换网络
公开(公告)号：US20080272806A1
公开(公告)日：2008-11-06
申请号：US12174080
申请日：2008-07-16
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/002 , H04L49/15 , H04L49/1515 , Y10T29/49002 , Y10T29/49117
摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
摘要翻译：具有开关和中间（级）导体的可扩展的非阻塞交换网络（SN），其用于在相应的互连资源约束内以大致无限制的方式将第一多个导体连接到其它多组导体。 SN可以应用在广泛的应用中，一起或分层，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 SN用于将第一组导体（通过SN）连接到给定逻辑电路层级中的多组导体，由此多个组中的每一个中的导体是等同的或可交换的，其在结构上使得当用于下一级电路层级时，第一组导体相当。 SN可针对大型导体组进行扩展，可以分级使用，以实现大尺寸电路之间的可编程互连。

14. 发明授权

US07417457B2 Scalable non-blocking switching network for programmable logic 有权
标题翻译：可编程逻辑的可扩展非阻塞交换网络
公开(公告)号：US07417457B2
公开(公告)日：2008-08-26
申请号：US11823257
申请日：2007-06-26
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/002 , H04L49/15 , H04L49/1515 , Y10T29/49002 , Y10T29/49117
摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth set of conductors. The SN is scalable for larger sets of conductors by adding additional sets of intermediate conductors in a hierarchically fashion.
摘要翻译：具有开关和中间（级））导体的可扩展非阻塞交换网络（SN），其用于将基本上第一组多个导体通过第一组开关连接到第二多组导体。第二组多个导体的每组中的导体通过第二组开关基本上连接到第三组多组导体。一组第三组多个导体中的每个导体在物理上连接到多个功能块中的每一个中的一个引脚，或者通过第三组开关连接到随后的第四组导体。 SN可以通过以分层方式添加额外的中间导体组来扩展更大的导体组。

15. 发明申请

US20080191739A1 Method and apparatus for universal program controlled bus architecture 审中-公开
标题翻译：通用程控总线架构的方法和装置
公开(公告)号：US20080191739A1
公开(公告)日：2008-08-14
申请号：US12148071
申请日：2008-04-15
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
摘要翻译：一种集成电路，其包括具有多个逻辑单元的可编程逻辑阵列和可编程互连以接收输入信号并执行发送输出信号的逻辑功能。集成电路还可以包括包括接收输入和发送输出的多个功能块的兆字节。集成电路还可以包括可级联子系统的可编程互连子系统。大功率器件耦合到可编程逻辑阵列。

16. 发明授权

US06975139B2 Scalable non-blocking switching network for programmable logic 有权
标题翻译：可编程逻辑的可扩展非阻塞交换网络
公开(公告)号：US06975139B2
公开(公告)日：2005-12-13
申请号：US10814943
申请日：2004-03-30
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19/177 , H04L12/56
CPC分类号： H03K19/17736 , H03K17/002 , H04L49/15 , H04L49/1515 , Y10T29/49002 , Y10T29/49117
摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, be construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
摘要翻译：具有开关和中间（级）导体的可扩展的非阻塞交换网络（SN），其用于在相应的互连资源约束内以大致无限制的方式将第一多个导体连接到其它多组导体。 SN可以应用在广泛的应用中，一起或分层，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 SN用于将第一组导体通过SN连接到给定逻辑电路层级中的多组导体，由此多组中的每一个中的导体是等效的或可交换的，其在构造中使得当用于下一级电路层级时，第一组导体相当。 SN可针对大型导体组进行扩展，可以分级使用，以实现大尺寸电路之间的可编程互连。

17. 发明授权

US6088526A Scalable multiple level tab oriented interconnect architecture 失效
标题翻译：可扩展的多级标签定向互连架构
公开(公告)号：US6088526A
公开(公告)日：2000-07-11
申请号：US951814
申请日：1997-10-14
申请人： Benjamin S. Ting , Peter M. Pani
发明人： Benjamin S. Ting , Peter M. Pani
IPC分类号： H03K19/173 , H03K19/177 , G06F15/20
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/17744 , H03K19/17792
摘要： An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of configurable function generators with lower levels of interconnect and for interfacing lower levels of interconnect with higher levels of interconnect. Furthermore, an innovative cluster architecture is utilized which provides fine granularity without a significant increase in configurable function generators. The tab connector network can also be used to route a lower level routing line to a higher level routing line. This is particularly desirable in order to meet the needs for driving a signal along longer routing lines without requiring all signal drivers be sufficiently large to drive a signal along the longest routing line. The connector networks described enable a flexible routing scheme to be implemented in which the routing lines at each level are divided into sets. In addition, the innovative routing hierarchy consisting of the routing lines, block connector tab networks and turn matrices, permits an innovative, space saving floor plan to be utilized that is scalable.
摘要翻译：提供了一种改进的现场可编程门阵列（FPGA），其包括用于将具有较低互连级别的可配置功能发生器组进行接口的接头网络连接器，以及用于将较低级别的互连与更高级别的互连连接。此外，利用创新的集群架构，其提供精细的粒度，而不会显着增加可配置的功能发生器。标签连接器网络也可用于将较低级别的路由选路线路由到较高级别的路由线路。这是特别期望的，以便满足沿较长路由线路驱动信号的需要，而不需要所有信号驱动器足够大以沿着最长路由线驱动信号。所描述的连接器网络使得能够实现灵活的路由方案，其中每个级别的路由线路被划分成一组。此外，由路由线，块连接器选项卡网络和转矩阵组成的创新路由层次结构允许利用可扩展的创新的节省空间的平面图。

18. 发明授权

US5850564A Scalable multiple level tab oriented interconnect architecture 失效
标题翻译：可扩展的多级标签定向互连架构
公开(公告)号：US5850564A
公开(公告)日：1998-12-15
申请号：US434980
申请日：1995-05-03
申请人： Benjamin S. Ting , Peter M. Pani
发明人： Benjamin S. Ting , Peter M. Pani
IPC分类号： H03K19/177 , G06F13/40
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17792 , H03K19/17796
摘要： A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2.times.2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4.times.4 block grouping to be scalable. The innovative floor plan makes efficient use of die space with little layout dead space as the floor plan provides for a plurality of contiguous memory and passgate arrays (which provide the functionality of the bidirectional switches) with small regions of logic for CFGs and drivers of the block connector tab networks. Therefore, the gaps typically incurred due to a mixture of memory and logic are avoided. Intra-cluster routing lines and bi-directional routing lines are overlayed on different layers of the chip together with memory and passgate arrays to provide connections to higher level routing lines and connections between CFGs in the block.
摘要翻译：一种可编程逻辑器件，其结合了由多层次的布线线，连接器标签网络和转向矩阵组成的创新路由层次结构，能够在集成电路实现中使用创新的节省空间的平面图，并且当SRAM 用作配置位该平面图是可扩展的块架构，其中将2x2块分组的每个块连接器选项卡网络相对于彼此沿相邻轴线布置为镜像。此外，双向输入/输出线被提供，因为每个块的输入/输出装置仅在两个方向（而不是典型的北，南，东和西方向）上取向，使得相邻块的块连接器标签网络面向相互取向。这种方向和布置允许块共享路由资源。此外，这种布置使得4×4块分组能够可扩展。创新的平面图计划有效地利用了具有很小的布局死空间的管芯空间，因为平面图为多个连续的存储器和通孔阵列（其提供双向开关的功能）提供了用于CFG的驱动器的小的逻辑区域阻止连接器选项卡网络。因此，避免了由于存储器和逻辑的混合引起的间隙。集群内路由线路和双向路由线路与芯片的不同层与存储器和传递门阵列重叠，以提供与较高级路由线路的连接以及块中CFG之间的连接。

19. 发明授权

US08106682B2 Permutable switching network with enhanced interconnectivity for multicasting signals 有权
标题翻译：具有增强的多播信号互联性的可互换交换网络
公开(公告)号：US08106682B2
公开(公告)日：2012-01-31
申请号：US12969419
申请日：2010-12-15
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H01L25/00
CPC分类号： H03K19/17736 , H01L21/768 , Y10T29/4913
摘要： In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
摘要翻译：在一个实施例中，集成电路具有包括L级中间导体的L电平可置换开关网络（L-PSN）。集成电路可用于电子设备，如交换网络，路由器和可编程逻辑电路等。

20. 发明申请

US20110084728A1 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS 有权
标题翻译：具有增强的互连信号的可互换切换网络
公开(公告)号：US20110084728A1
公开(公告)日：2011-04-14
申请号：US12969419
申请日：2010-12-15
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L21/768 , Y10T29/4913
摘要： In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
摘要翻译：在一个实施例中，集成电路具有包括L级中间导体的L电平可置换开关网络（L-PSN）。集成电路可用于电子设备，如交换网络，路由器和可编程逻辑电路等。

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