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11. 发明授权

US07671858B1 Unconstrained paving and plastering method for generating finite element meshes 有权
标题翻译：用于生成有限元网格的无约束铺路和抹灰方法
公开(公告)号：US07671858B1
公开(公告)日：2010-03-02
申请号：US11515978
申请日：2006-09-05
申请人： Matthew L. Staten , Steven J. Owen , Teddy D. Blacker , Robert Kerr
发明人： Matthew L. Staten , Steven J. Owen , Teddy D. Blacker , Robert Kerr
IPC分类号： G06T15/00
CPC分类号： G06T17/20 , G06T17/10
摘要： Computer software for and a method of generating a conformal all quadrilateral or hexahedral mesh comprising selecting an object with unmeshed boundaries and performing the following while unmeshed voids are larger than twice a desired element size and unrecognizable as either a midpoint subdividable or pave-and-sweepable polyhedra: selecting a front to advance; based on sizes of fronts and angles with adjacent fronts, determining which adjacent fronts should be advanced with the selected front; advancing the fronts; detecting proximities with other nearby fronts; resolving any found proximities; forming quadrilaterals or unconstrained columns of hexahedra where two layers cross; and establishing hexahedral elements where three layers cross.
摘要翻译：包括计算机软件和生成保形全四边形或六面体网格的方法，包括选择具有非网格边界的对象，并执行以下操作，而非网格空洞大于所需元素大小的两倍，并且无法识别为可分割中点或可铺平面多面体：选择前方前进; 基于相邻前沿的角度和角度，确定哪个相邻的前端应与所选择的前部前进; 推进战线检测与其他附近阵线的近距离; 解决任何发现的接近度; 形成四面体或六角形的无约束柱，其中两层交叉; 并建立三层交叉的六面体元素。

12. 发明申请

US20060010040A1 System and method for collecting and transmitting medical data 失效
公开(公告)号：US20060010040A1
公开(公告)日：2006-01-12
申请号：US11222157
申请日：2005-09-07
申请人： Robert Kerr
发明人： Robert Kerr
IPC分类号： G06G1/14
CPC分类号： G06F19/3418 , A61B5/0002 , G06F19/00 , G06Q20/203 , G06Q50/22 , G16H10/20
摘要： A system and method for collecting and transmitting medical and health-related data over a network are disclosed. A measuring device measures a user's physiological attribute and produces a first signal related thereto, which an integration system coupled to the measuring device receives and converts into a second signal for transmitting over the Internet. In accordance with one aspect of a preferred embodiment, the integration system is adapted to read the first signal as it is sent from the measuring device to its display. A communications system transmits the second signal over the Internet to a remote system using any of a variety of techniques known in the art. The remote system extracts the measured physiological attribute and other associated data from the second signal and populates a database. Preferably, a web-based portal provides access to the data for one or more users.

13. 发明授权

US06784502B2 Method of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits 有权
标题翻译：形成触点的方法，接触线的方法，操作集成电路的方法和集成电路
公开(公告)号：US06784502B2
公开(公告)日：2004-08-31
申请号：US09512978
申请日：2000-02-24
申请人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
发明人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2976
CPC分类号： H01L27/10897 , H01L21/76895 , H01L23/535 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.
摘要翻译：描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。导电触点形成在接触开口内并与各个接触垫电连接。在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

14. 发明授权

US06380023B2 Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits 失效
标题翻译：形成触点的方法，接触线的方法，操作集成电路的方法和集成电路
公开(公告)号：US06380023B2
公开(公告)日：2002-04-30
申请号：US09146115
申请日：1998-09-02
申请人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
发明人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L218234
CPC分类号： H01L27/10897 , H01L21/76895 , H01L23/535 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.
摘要翻译：描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。导电触点形成在接触开口内并与各个接触垫电连接。在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

15. 发明授权

US06215151B1 Methods of forming integrated circuitry and integrated circuitry 有权
标题翻译：形成集成电路和集成电路的方法
公开(公告)号：US06215151B1
公开(公告)日：2001-04-10
申请号：US09255667
申请日：1999-02-23
申请人： Zhiqiang Wu , Luan C. Tran , Robert Kerr , Shubneesh Batra , Rongsheng Yang
发明人： Zhiqiang Wu , Luan C. Tran , Robert Kerr , Shubneesh Batra , Rongsheng Yang
IPC分类号： H01L27148
CPC分类号： H01L21/823807
摘要： Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.
摘要翻译：描述了形成集成电路的集成电路和方法。在一个实现中，利用公共掩模步骤来相对于衬底的一个阱区域内的源极/漏极区域提供源极/漏极扩散区域和晕圈离子注入或掺杂区域; 以及在衬底的另一个阱区域内的良好接触扩散区域。常见的掩蔽步骤优选地限定在其上将要形成阱接触扩散区的衬底上的至少一个掩模开口，并且掩模开口被适当地设定尺寸以减少最终到达衬底的卤素离子注入掺杂剂的量。根据一个方面，提供了多个掩模开口。根据另一方面，提供了适当尺寸的单个掩模开口。在另一方面，独特的井区结构设置有一个或多个互补掩模开口，其被配置为与提供卤素离子注入掺杂剂相结合，阻止最终到达衬底的注入掺杂剂的量邻近阱接触扩散区。因此，在用卤素离子注入掺杂剂掺杂衬底之后，至少一些阱接触扩散区域保持与阱区基本接触。

16. 发明授权

US09123784B2 Memory process and memory structure made thereby 有权
标题翻译：由此产生的内存进程和内存结构
公开(公告)号：US09123784B2
公开(公告)日：2015-09-01
申请号：US13590204
申请日：2012-08-21
申请人： Vivek Gopalan , Robert Kerr , Hung-Ming Tsai
发明人： Vivek Gopalan , Robert Kerr , Hung-Ming Tsai
IPC分类号： H01L27/108 , H01L21/768
CPC分类号： H01L21/76883 , H01L21/76802 , H01L27/108 , H01L27/10891
摘要： A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
摘要翻译：描述记忆过程。提供了一种衬底，其中具有埋在沟槽中的沟槽和导线，并且具有阵列区域，其中每条导线在阵列区域中具有阵列部分。在基板上限定与阵列区域分开的接触区域，其中每个导线在接触区域中具有接触部分。导电线的接触部分之间的衬底被蚀刻到导电层的顶部之下，以在导电线的接触部分之间形成间隙。然后用绝缘层填充该间隙。

17. 发明申请

US20130161700A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE 有权
标题翻译：在存储器件上制造侧壁间隔的方法
公开(公告)号：US20130161700A1
公开(公告)日：2013-06-27
申请号：US13335578
申请日：2011-12-22
申请人： Panda Durga , Jaydip Guha , Robert Kerr
发明人： Panda Durga , Jaydip Guha , Robert Kerr
IPC分类号： H01L27/118 , H01L21/311
CPC分类号： H01L29/6656 , H01L21/02164 , H01L21/0217 , H01L21/31111 , H01L21/823431 , H01L27/105 , H01L27/1052 , H01L27/10844 , H01L27/10873 , H01L27/10894 , H01L29/6653
摘要： The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
摘要翻译：本发明涉及在存储器件上制造侧壁间隔物的方法。该方法包括：在具有存储器阵列区域和至少一个外围电路区域的存储器件上形成侧壁间隔物，通过形成与存储器阵列区域中的字线相邻的第一侧壁间隔件和与外围晶体管相邻的第二侧壁间隔物电路区域。第一侧壁间隔件具有第一厚度，并且第二侧壁间隔件具有第二厚度，其中第二厚度大于第一厚度。

18. 发明授权

US07347114B2 Template 失效
标题翻译：模板
公开(公告)号：US07347114B2
公开(公告)日：2008-03-25
申请号：US11085772
申请日：2005-03-21
申请人： Herbert M Reynolds , Robert Kerr , Raymond Brodeur , Khaldoun Rayes , Douglas Neal , Yuntao Cui
发明人： Herbert M Reynolds , Robert Kerr , Raymond Brodeur , Khaldoun Rayes , Douglas Neal , Yuntao Cui
IPC分类号： G01M19/00
CPC分类号： B60N3/00 , A47C31/126
摘要： A design template includes a torso section being one of a group of a 95th percentile male, 50th percentile male and 5th female having each being one of a group of an ERECT posture, a NEUTRAL posture and a SLUMPED posture.
摘要翻译：设计模板包括躯体部分，其是具有每个的第95个百分位男性，第50个百分位数男性和第五个女性的一组中的一个作为ERECT姿势，中立姿势和SLUMPED姿势的组之一。

19. 发明授权

US06759288B2 Double LDD devices for improved DRAM refresh 失效
标题翻译：双LDD器件可改善DRAM刷新
公开(公告)号：US06759288B2
公开(公告)日：2004-07-06
申请号：US10208830
申请日：2002-08-01
申请人： Luan C. Tran , Mark McQueen , Robert Kerr
发明人： Luan C. Tran , Mark McQueen , Robert Kerr
IPC分类号： H01L21337
CPC分类号： H01L27/10894 , H01L27/10897 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.
摘要翻译：提供了具有改进的DRAM刷新特性的集成电路器件，以及制造该器件的新颖方法。半导体基板在阵列部分和周边部分中的表面上设置有栅极结构。单个轻掺杂区域通过在衬底中的离子注入形成在沟道区附近。具有第一宽度的电介质间隔物形成在与覆盖单个轻掺杂区域的至少一部分的栅极结构相邻的衬底表面上。重掺杂区域被离子注入在外围部分中的栅极结构的相对侧上。电介质间隔物被回蚀到小于第一宽度的第二宽度。通过离子注入形成双重轻掺杂区域，该衬底在衬底的由间隔物回蚀刻暴露的区域中。三个轻掺杂区域也可以通过在栅极边缘处的第一注入，通过中间间隔物的第二植入物和间隔物回蚀后的第三植入物形成。

20. 发明授权

US06455362B1 Double LDD devices for improved dram refresh 有权
标题翻译：双LDD设备，可改善电脑刷新
公开(公告)号：US06455362B1
公开(公告)日：2002-09-24
申请号：US09642780
申请日：2000-08-22
申请人： Luan C. Tran , Mark McQueen , Robert Kerr
发明人： Luan C. Tran , Mark McQueen , Robert Kerr
IPC分类号： H01L21337
CPC分类号： H01L27/10894 , H01L27/10897 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.
摘要翻译：提供了具有改进的DRAM刷新特性的集成电路器件，以及制造该器件的新颖方法。半导体基板在阵列部分和周边部分中的表面上设置有栅极结构。单个轻掺杂区域通过在衬底中的离子注入形成在沟道区附近。具有第一宽度的电介质间隔物形成在与覆盖单个轻掺杂区域的至少一部分的栅极结构相邻的衬底表面上。重掺杂区域被离子注入在外围部分中的栅极结构的相对侧上。电介质间隔物被回蚀到小于第一宽度的第二宽度。通过离子注入形成双重轻掺杂区域，该衬底在衬底的由间隔物回蚀刻暴露的区域中。三个轻掺杂区域也可以通过在栅极边缘处的第一注入，通过中间间隔物的第二植入物和间隔物回蚀后的第三植入物形成。

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