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11. 发明授权

US07450454B1 Low voltage data path in memory array 有权
标题翻译：存储器阵列中的低电压数据通路
公开(公告)号：US07450454B1
公开(公告)日：2008-11-11
申请号：US11746126
申请日：2007-05-09
申请人： Maciej Bajkowski , Hamed Ghassemi , Huy B. Nguyen
发明人： Maciej Bajkowski , Hamed Ghassemi , Huy B. Nguyen
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1069
摘要： A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.
摘要翻译：存储器的数据路径来自存储器的阵列，通过读出放大器，通过NOR门，通过N沟道晶体管，以及通过提供输出的锁存器。读出放大器向NOR门提供互补数据，这些数字向N沟道晶体管提供输出。 NOR门向锁存器提供输出。这具有向一个逆变器的栅极和另一个逆变器的漏极提供输出的影响。附加的P沟道晶体管与锁存器的反相器串联。与漏极接收信号的反相器串联的P沟道晶体管被非门的输出导通，以阻止向提供输入到锁存器的N沟道晶体管的电流流动。电流的阻塞减小了N沟道晶体管必须吸收的电流量。这使得即使在降低的电压下，N沟道晶体管也能充分导通以翻转锁存器的状态。

12. 发明申请

US20080186797A1 CIRCUIT FOR USE IN A MULTIPLE BLOCK MEMORY 有权
标题翻译：用于多个块存储器的电路
公开(公告)号：US20080186797A1
公开(公告)日：2008-08-07
申请号：US11672279
申请日：2007-02-07
申请人： Hamed Ghassemi , Huy B. Nguyen
发明人： Hamed Ghassemi , Huy B. Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G06F12/0893 , G11C7/106 , G11C8/12 , G11C2207/2245
摘要： A portion of a memory may include a first memory block, comprising a first memory cell coupled to a first memory data line, a second memory block, comprising a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.
摘要翻译：存储器的一部分可以包括第一存储器块，其包括耦合到第一存储器数据线的第一存储器单元，第二存储器块，包括耦合到第二存储器数据线的第二存储器单元，以及锁存器，终端和第二终端。存储器的部分还可以包括第一N沟道晶体管，其具有耦合到锁存器的第一端的第一电流电极，具有耦合到第一电源电压的第二电流电极，并且具有耦合到第一个内存数据线。存储器的部分还可以包括第二N沟道晶体管，其具有耦合到锁存器的第一端的第一电流电极，具有耦合到第一电源电压的第二电流电极，并且具有耦合到第一电源电压的控制电极第二存储器数据线。

13. 发明申请

US20080054980A1 LEVEL SHIFTING CIRCUIT 有权
标题翻译：水平移位电路
公开(公告)号：US20080054980A1
公开(公告)日：2008-03-06
申请号：US11468815
申请日：2006-08-31
申请人： Maciej Bajkowski , George P. Hoekstra , Hamed Ghassemi
发明人： Maciej Bajkowski , George P. Hoekstra , Hamed Ghassemi
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/356121
摘要： A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.
摘要翻译：电平移动电路，其具有在第一电压域中操作的信号输入和在第二电压域中操作的信号输出。在一些实施例中，电平移位电路包括时钟电平移位器。在一些实施例中，电平移位电路包括锁存转换的输出信号的电平移位锁存器。在一个示例中，电平移位锁存器包括具有耦合到时钟输入的控制电极的晶体管的锁存部分和晶体管堆叠。

14. 发明授权

US07443223B2 Level shifting circuit 有权
标题翻译：电平转换电路
公开(公告)号：US07443223B2
公开(公告)日：2008-10-28
申请号：US11468815
申请日：2006-08-31
申请人： Maciej Bajkowski , George P. Hoekstra , Hamed Ghassemi
发明人： Maciej Bajkowski , George P. Hoekstra , Hamed Ghassemi
IPC分类号： H03K19/0175
CPC分类号： H03K19/01855 , H03K3/356121
摘要： A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.
摘要翻译：电平移动电路，其具有在第一电压域中操作的信号输入和在第二电压域中操作的信号输出。在一些实施例中，电平移位电路包括时钟电平移位器。在一些实施例中，电平移位电路包括锁存转换的输出信号的电平移位锁存器。在一个示例中，电平移位锁存器包括具有耦合到时钟输入的控制电极的晶体管的锁存部分和晶体管堆叠。

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