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11. 发明授权

US11048516B2 Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array 有权
公开(公告)号：US11048516B2
公开(公告)日：2021-06-29
申请号：US14752891
申请日：2015-06-27
申请人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
发明人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
IPC分类号： G06F9/38 , G06F9/30
摘要： Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.

12. 发明授权

US08732438B2 Anti-prefetch instruction 有权
标题翻译：反预取指令
公开(公告)号：US08732438B2
公开(公告)日：2014-05-20
申请号：US12104159
申请日：2008-04-16
申请人： Paul Caprioli , Sherman H. Yip , Gideon N. Levinsky
发明人： Paul Caprioli , Sherman H. Yip , Gideon N. Levinsky
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F12/0862
摘要： Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.
摘要翻译：本发明的实施例执行反预取指令。这些实施例首先解码处理器中的解码单元中的指令，以准备执行指令。在对反预取指令进行解码时，这些实施例使解码单元停止以防止解码后续指令。这些实施例然后执行反预取指令，其中执行反预取指令涉及：（1）在L1高速缓存中发送用于高速缓存行的预取请求; （2）确定预取请求是否在L1高速缓存中命中; （3）如果预取请求命中在L1高速缓存中，则确定高速缓存线是否包含预定值; 以及（4）基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

13. 发明申请

US20130283249A1 INSTRUCTION AND LOGIC TO PERFORM DYNAMIC BINARY TRANSLATION 有权
标题翻译：指令和逻辑执行动态二进制翻译
公开(公告)号：US20130283249A1
公开(公告)日：2013-10-24
申请号：US13995400
申请日：2011-09-30
申请人： Abhay S. Kanhere , Paul Caprioli , Koichi Yamada , Suriya Madras-Subramanian , Suresh Srinivas
发明人： Abhay S. Kanhere , Paul Caprioli , Koichi Yamada , Suriya Madras-Subramanian , Suresh Srinivas
IPC分类号： G06F9/45
CPC分类号： G06F8/40 , G06F8/456 , G06F8/51 , G06F9/30109 , G06F9/30185 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3877 , G06F9/3887 , G06F9/4552
摘要： A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
摘要翻译：微架构可以提供硬件和软件协同设计的动态二进制翻译。微架构可以调用执行动态二进制转换的方法。该方法可以包括执行针对第一指令集编译的原始软件代码，使用处理器硬件来检测软件代码中的热点并将控制传递给二进制翻译翻译器，确定用于翻译的热点区域，使用第二指令集，将转换的代码放置在转换高速缓存中，从翻译的高速缓存中执行转换的代码，并且在转换的代码完成执行之后转换回原始软件代码。

14. 发明授权

US08484434B2 Index generation for cache memories 有权
标题翻译：高速缓存存储器的索引生成
公开(公告)号：US08484434B2
公开(公告)日：2013-07-09
申请号：US13402796
申请日：2012-02-22
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F13/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

15. 发明授权

US08161273B2 Method and apparatus for programmatically rewinding a register inside a transaction 有权
标题翻译：用于在事务中以程序方式倒回寄存器的方法和装置
公开(公告)号：US08161273B2
公开(公告)日：2012-04-17
申请号：US12037636
申请日：2008-02-26
申请人： Paul Caprioli
发明人： Paul Caprioli
IPC分类号： G06F9/308 , G06F9/312
CPC分类号： G06F9/30123 , G06F9/3004 , G06F9/30087 , G06F9/3013 , G06F9/30145 , G06F9/3834 , G06F9/3863 , G06F9/462
摘要： Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving a pre-transactional state of registers in a first register file. The system then allocates one or more registers for temporary use during the transaction. Upon finishing using each allocated register during the transaction, the system executes an instruction that restores the allocated register to the pre-transactional state.
摘要翻译：本发明的实施例提供一种在处理器中分配寄存器的系统。系统从开始事务开始，其中开始事务涉及在第一寄存器文件中保留寄存器的事务前状态。然后系统在事务期间分配一个或多个临时使用的寄存器。一旦完成了在交易过程中使用每个分配的寄存器，系统将执行将所分配的寄存器恢复到事务前状态的指令。

16. 发明授权

US07890739B2 Method and apparatus for recovering from branch misprediction 有权
标题翻译：从分支错误预测中恢复的方法和装置
公开(公告)号：US07890739B2
公开(公告)日：2011-02-15
申请号：US12033626
申请日：2008-02-19
申请人： Paul Caprioli
发明人： Paul Caprioli
IPC分类号： G06F9/42
CPC分类号： G06F9/3861 , G06F9/383
摘要： Embodiments of the present invention provide a system that executes a branch instruction. When executing the branch instruction, the system obtains a stored prediction of a resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction. If an actual resolution of the branch instruction is different from the predicted resolution (i.e., if the branch is mispredicted), the system updates the stored prediction of the resolution of the branch instruction to the actual resolution of the branch instruction. The system then re-executes the branch instruction. When re-executing the branch instruction, the system obtains the stored prediction of the resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction.
摘要翻译：本发明的实施例提供一种执行分支指令的系统。当执行分支指令时，系统获得存储的分支指令的分辨率的预测，并且基于分支指令的预测分辨率获取后续的执行指令。如果分支指令的实际分辨率与预测分辨率不同（即，如果分支被错误预测），则系统将存储的分支指令的分辨率的预测更新为分支指令的实际分辨率。然后系统重新执行分支指令。当重新执行分支指令时，系统获得存储的分支指令的分辨率的预测，并且基于分支指令的预测分辨率获取后续的执行指令。

17. 发明申请

US20100161950A1 SEMI-ABSOLUTE BRANCH INSTRUCTIONS FOR EFFICIENT COMPUTERS 审中-公开
标题翻译：用于高效计算机的半绝对分支指令
公开(公告)号：US20100161950A1
公开(公告)日：2010-06-24
申请号：US12344151
申请日：2008-12-24
申请人： Paul Caprioli , Peter B. Kessler , Christopher A. Vick
发明人： Paul Caprioli , Peter B. Kessler , Christopher A. Vick
IPC分类号： G06F9/30
CPC分类号： G06F9/322 , G06F9/324
摘要： Apparatus and methods are disclosed for a computation processor that can execute a semi-absolute branch instruction, as well as methods of operation and of generating the semi-absolute branch instruction.
摘要翻译：公开了一种可以执行半绝对分支指令的计算处理器以及操作方法和生成半绝对分支指令的装置和方法。

18. 发明授权

US07610470B2 Preventing register data flow hazards in an SST processor 有权
标题翻译：防止SST处理器中的寄存器数据流危害
公开(公告)号：US07610470B2
公开(公告)日：2009-10-27
申请号：US11703462
申请日：2007-02-06
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863
摘要： One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register is subject to an unresolved data dependency. Upon the resolution of a data dependency during execute-ahead mode, the system copies dependency information to a speculative copy of the dependency information. The system then commences execution of the deferred instructions in a deferred mode using a second thread. While executing instructions in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a write-after-write (WAW) hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the system uses the second thread to execute the deferred instruction to produce a result and forwards the result to be used by subsequent deferred instructions without committing the result to the architectural state of the destination register. Hence, the system makes the result available to the subsequent deferred instructions without overwriting the result produced by a following non-deferred instruction.
摘要翻译：本发明的一个实施例提供一种在同时推测的线程中防止数据危害的系统。系统通过使用第一个线程以执行模式执行指令来启动。在执行执行模式下执行指令时，系统维护每个寄存器的依赖信息，指示寄存器是否受到未解析的数据依赖。在执行提前模式下解析数据依赖关系时，系统将依赖关系信息复制到依赖关系信息的推测性副本。然后，系统使用第二个线程以延迟模式开始执行延迟指令。在延迟模式下执行指令时，如果目的寄存器的依赖关系信息的推测性副本指示在执行提前模式下由第一线程执行的后续非延迟指令存在写后写入（WAW）危险，系统使用第二个线程执行延迟指令以产生结果，并转发后续延迟指令使用的结果，而不将结果提交到目标寄存器的体系结构状态。因此，系统使结果可用于后续延期指令，而不会覆盖由以下非延迟指令产生的结果。

19. 发明授权

US07571304B2 Generation of multiple checkpoints in a processor that supports speculative execution 有权
标题翻译：在支持推测性执行的处理器中生成多个检查点
公开(公告)号：US07571304B2
公开(公告)日：2009-08-04
申请号：US11084655
申请日：2005-03-18
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3842
摘要： One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint.
摘要翻译：本发明的一个实施例提供一种在支持推测执行的处理器中创建多个检查点的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在使处理器进入执行模式的指令期间遇到启动条件时，系统执行初始检查点并以执行提前模式开始执行指令。在执行提前模式期间遇到预定义的条件时，系统生成附加检查点，并以执行提前模式继续执行指令。如果处理器随后遇到需要处理器返回到检查点的条件，则生成附加检查点将允许处理器返回到附加检查点，而不是先前检查点。

20. 发明授权

US07421465B1 Arithmetic early bypass 有权
标题翻译：算术早期绕行
公开(公告)号：US07421465B1
公开(公告)日：2008-09-02
申请号：US10932522
申请日：2004-09-02
申请人： Leonard Dennis Rarick , Murali Krishna Inaganti , Shailender Chaudhry , Paul Caprioli
发明人： Leonard Dennis Rarick , Murali Krishna Inaganti , Shailender Chaudhry , Paul Caprioli
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： A value that bypasses some of the computations for an arithmetic operation can be supplied for performance of a dependent arithmetic operation without waiting for completion of the computations of the arithmetic operation. During performance of a first arithmetic operation, a value is generated. The value is viable for use in performing a second arithmetic operation that is dependent upon the first arithmetic operation. The value is utilized to continue performance of the first arithmetic operation and commence performance of the second arithmetic operation. As part of the continued performance of the first arithmetic operation, determining whether the value is to be modified for the first arithmetic operation. Compensating for modifications to the value for performance of the second arithmetic operation.
摘要翻译：可以提供绕过算术运算的一些计算的值，以执行相关的算术运算，而无需等待算术运算的计算完成。在执行第一个算术运算时，产生一个值。该值对于用于执行依赖于第一算术运算的第二算术运算来说是可行的。该值用于继续执行第一算术运算并开始执行第二算术运算。作为继续执行第一算术运算的一部分，确定是否要为第一算术运算修改该值。补偿修改第二个算术运算的性能值。

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