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11. 发明专利

GB2370381B Processor architecture 未知
公开(公告)号：GB2370381B
公开(公告)日：2003-12-24
申请号：GB0030994
申请日：2000-12-19
申请人： PICOCHIP DESIGNS LTD
发明人： CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F7/00 , G06F1/32 , G06F9/38 , G06F13/36 , G06F15/80 , G06F15/173
摘要： A processor architecture includes a plurality of processing elements and a bus structure. Each element has at least one input port and at least one output port, each port having at least a data bus and a valid data signal line. The bus structure contains a plurality of switches arranged to connect an output port of any first processing element to the input port of any second processing element for a time interval. Each processing element sets a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value and to a second logic state when it does not contain a transfer value. Each processing element enters a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state.

12. 发明专利

AU9407301A Processor architecture 未知
公开(公告)号：AU9407301A
公开(公告)日：2002-07-01
申请号：AU9407301
申请日：2001-10-19
申请人： PICOCHIP DESIGNS LTD
发明人： CLAYDON ANTHONY PETER JOHN , CLAYDON ANNE PATRICIA
IPC分类号： G06F7/00 , G06F15/80

13. 发明专利

GB2370380A A processor element array with switched matrix data buses 未知
公开(公告)号：GB2370380A
公开(公告)日：2002-06-26
申请号：GB0030993
申请日：2000-12-19
申请人： PICOCHIP DESIGNS LTD
发明人： CLAYDON ANTHONY PETER JOHN , CLAYDON ANNE PATRICIA
IPC分类号： G06F7/00 , G06F15/80 , G06F15/173
摘要： An array of processor elements 20 is intra-connected via a network of data buses 32, 36 and 42, 46 (30, 40 Fig 1) and switch matrices 55. The data buses are unidirectional (they contain MUXes within their paths) and run in cross matched pairs (left and right 36, 32; up and down 42 46). The buses intersect at switch matrices(constructed from 4:1 multiplexers) which allow for directing of data signals. Several types of processor elements are used, such as ALU, MAC, memory, switch controller and interface elements (Fig 5). The array elements are data driven in that they execute an instruction as a result of receiving data. The processor is suited to digital signal processing (DSP) applications and has power saving features useful when used in applications such as hand held devices.

14. 发明专利

GB2398650B Communications in a processor array 未知
公开(公告)号：GB2398650B
公开(公告)日：2006-09-20
申请号：GB0304055
申请日：2003-02-21
申请人： PICOCHIP DESIGNS LTD
发明人： PANESAR GAJINDER , CLAYDON ANTHONY PETER JOHN , ROBBINS WILLIAM PHILIP , ORR ALEX , DULLER ANDREW
IPC分类号： G06F13/14 , G06F15/173 , G06F20060101 , G06F13/38 , G06F13/42 , G06F15/80
摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.

15. 发明专利

GB2391083B Processor array 未知
公开(公告)号：GB2391083B
公开(公告)日：2006-03-01
申请号：GB0216880
申请日：2002-07-19
申请人： PICOCHIP DESIGNS LTD
发明人： ROBBINS WILLIAM , DAVISON MICHAEL , HOWELL SIMON , CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F11/20 , G11C29/00 , G06F15/80
摘要： An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.

16. 发明专利

GB2391083A A processor array with redundancy in which functionality is removed from a row containing a faulty processing element 未知
公开(公告)号：GB2391083A
公开(公告)日：2004-01-28
申请号：GB0216880
申请日：2002-07-19
申请人： PICOCHIP DESIGNS LTD
发明人： ROBBINS WILLIAM , DAVISON MICHAEL , HOWELL SIMON , CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F11/20 , G06F15/80 , G11C29/00
摘要： A processor array, or method, comprising a plurality of processor elements AExx (20, in figure 1, which may be only memory devices), buses 41, 42 (and 41-44, 32, 36 in figure 1) and switches SWxx wherein the processor elements AExx form rows and columns and are interconnected by buses, switches being placed at the bus intersections; such that in the event that a processing element AExx is found to be faulty no functionality is allocated to any processing element in its row 45. Preferably a redundant row of processor elements is used to functionally replace a faulty row, the bus structure being designed to accommodate this replacement. The replacement can either be performed by switching from a faulty row to a redundant row or by switching a first (faulty) rows functionality to a second adjacent row then switching this second row with a further row, and so on, until the redundant row is used. Also disclosed is a processor array in which all rows of processing elements are the same and pairs of horizontal buses carrying data in opposite directions are provided between the rows and two pairs of vertical buses carrying data in opposite directions are provided between some of the colunms. The invention is used to allow useful products to be created despite point defects in wafers (figure 4) and also to allow operational faults to be bypassed.

17. 发明专利

GB2370381A A processor element array with switched matrix data buses 未知
公开(公告)号：GB2370381A
公开(公告)日：2002-06-26
申请号：GB0030994
申请日：2000-12-19
申请人： PICOCHIP DESIGNS LTD
发明人： CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F7/00 , G06F1/32 , G06F9/38 , G06F13/36 , G06F15/80 , G06F15/173
摘要： An array of processor elements 20 is intra-connected via a network of data buses 32, 36 and 42, 46 (30, 40 Fig 1) and switch matrices 55. The data buses are unidirectional (they contain MUXes within their paths) and run in cross matched pairs (left and right 36, 32; up and down 42 46). The buses intersect at switched matrices(constructed from 4:1 multiplexers) which allow for directing of data signals. Several types of processor elements are used such as ALU, MAC, memory, switch controller and interface elements (Fig 5). The array elements are data driven in that they execute an instruction as a result of receiving data. Each input port of the processing elements has an associated valid data signal line used to indicate when the input bus contains valid data. The processor elements enter a waiting state (sleep) when there is no valid data on their input data bus. The processor is suited to digital signal processing (DSP) applications and has power saving features useful when used in hand held devices.

18. 发明专利

GB2417586A A processor array with pairs of horizontal and vertical buses and with row redundancy 未知
公开(公告)号：GB2417586A
公开(公告)日：2006-03-01
申请号：GB0520346
申请日：2002-07-19
申请人： PICOCHIP DESIGNS LTD
发明人： DAVISON MICHAEL , HOWELL SIMON , ROBBINS WILLIAM , CLAYDON ANTHONY PETER JOHN
IPC分类号： G11C29/00 , G06F11/20 , G06F15/80
摘要： A processor array has rows of processing elements in which all rows are the same. Pairs of horizontal buses (32, 36, figure 1) carrying data in opposite directions are provided between the rows and pairs of vertical buses 41, 42 carrying data in opposite directions are provided between some but not all of the columns. Switches 55 are provided at the intersections of vertical and horizontal buses, each switch including a memory device indicating which data is to be switched and a controller. Also disclosed is a redundancy system such that when a processing element is found faulty no functionality is assigned to that processing element. A redundant row or processing elements is used instead of the row with the faulty element. The replacement can either be performed by switching from a faulty row to a redundant row or by switching a first (faulty) row's functionality to an adjacent row, then switching this second row, and so on until the redundant row is used.

19. 发明专利

GB2398650A Communications in a processor array 未知
公开(公告)号：GB2398650A
公开(公告)日：2004-08-25
申请号：GB0304055
申请日：2003-02-21
申请人： PICOCHIP DESIGNS LTD
发明人： PANESAR GAJINDER , CLAYDON ANTHONY PETER JOHN , ROBBINS WILLIAM PHILIP , ORR ALEX , DULLER ANDREW
IPC分类号： G06F13/14 , G06F20060101 , G06F13/38 , G06F13/42 , G06F15/173 , G06F15/80
摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data. If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.

20. 发明专利

ES2285191T3 CONJUNTO ORDENADO DE PROCESADORES. 未知
公开(公告)号：ES2285191T3
公开(公告)日：2007-11-16
申请号：ES03765145
申请日：2003-06-27
申请人： PICOCHIP DESIGNS LTD
发明人： ROBBINS WILLIAM , DAVIDSON MICHAEL , HOWELL SIMON , CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F15/80 , G06F11/20 , G11C29/00
摘要： Un método para asignar funcionalidad a elementos procesadores (20) en un conjunto ordenado de procesadores, en el que el conjunto ordenado de procesadores comprende una pluralidad de elementos procesadores (20) dispuestos en un conjunto ordenado de filas y columnas, estando interconectados los elementos procesadores (20) por buses (32, 36, 41-44) que se extienden entre las filas y las columnas y mediante conmutadores (55) situados en las intersecciones de los buses (32, 36, 41-44), en el que, en el funcionamiento de dicha ordenación de procesadores, se transfieren datos durante intervalos de tiempo entre elementos procesadores (20) sobre buses horizontales (32-36) que se extienden entre las filas de elementos procesadores (20) y sobre buses verticales (41-44) que se extienden entre las columnas de elementos procesadores (20), comprendiendo el método: identificar una fila como una fila redundante a la que no se asigna funcionalidad inicialmente, de modo que en el caso en que se encuentre unprimer elemento procesador defectuoso, la funcionalidad puede ser eliminada de la fila que contiene dicho primer elemento de tratamiento, y puede ser asignada a la fila redundante; cuando se asigna funcionalidad a los elementos procesadores, de modo que los datos son programados para ser transferidos durante un primer intervalo de tiempo desde un primer elemento procesador en una primera fila a un segundo elemento procesador en una segunda fila, que es diferente de la primera fila, a través de uno de dichos conmutadores sin usar bus vertical alguno, reservando dicho intervalo de tiempo para transferir dichos datos programados sobre un segmento de un bus vertical que serían usados en el caso de una reasignación de funcionalidad siguiente a una determinación de que dicho primer elemento procesador o dicho segundo elemento procesador estaba averiado.

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