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11. 发明授权

US08686411B2 Methods of self-aligned growth of chalcogenide memory access device 有权
公开(公告)号：US08686411B2
公开(公告)日：2014-04-01
申请号：US13837736
申请日：2013-03-15
申请人： Neil Greeley , Bhaskar Srinivasan , Gurtej Sandhu , John Smythe
发明人： Neil Greeley , Bhaskar Srinivasan , Gurtej Sandhu , John Smythe
IPC分类号： H01L29/06
CPC分类号： H01L27/2481 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1608 , H01L45/165 , H01L45/1658 , H01L45/1683
摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

12. 发明申请

US20120241911A1 METHODS OF SELF-ALIGNED GROWTH OF CHALCOGENIDE MEMORY ACCESS DEVICE 有权
标题翻译： CHALCOGENIDE MEMORY ACCESS DEVICE的自对准生长方法
公开(公告)号：US20120241911A1
公开(公告)日：2012-09-27
申请号：US13491165
申请日：2012-06-07
申请人： Neil Greeley , Bhaskar Srinivasan , Gurtej Sandhu , John Smythe
发明人： Neil Greeley , Bhaskar Srinivasan , Gurtej Sandhu , John Smythe
IPC分类号： H01L29/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1608 , H01L45/165 , H01L45/1658 , H01L45/1683
摘要： Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.
摘要翻译：用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。该方法可用于形成三维堆叠的交叉点存储器阵列。该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

13. 发明授权

US08845812B2 Method for contamination removal using magnetic particles 有权
标题翻译：使用磁性颗粒去除污染物的方法
公开(公告)号：US08845812B2
公开(公告)日：2014-09-30
申请号：US12483518
申请日：2009-06-12
申请人： Nishant Sinha , Steve Kramer , Gurtej Sandhu
发明人： Nishant Sinha , Steve Kramer , Gurtej Sandhu
IPC分类号： B08B7/00
CPC分类号： H01L21/6704 , B03C1/01 , B03C2201/16 , B03C2201/20 , B08B3/10 , C11D3/1206 , C11D3/1213 , C11D7/20 , C11D17/0013 , H01L21/67028
摘要： Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from a surface of the substrate.
摘要翻译：提供的方法和装置用于在半导体器件的制造中清洗衬底（例如，晶片），该半导体器件利用分散在基础流体内的磁性颗粒的组合物从衬底的表面去除污染物。

14. 发明申请

US20100313907A1 Method and Apparatus for Contamination Removal Using Magnetic Particles 有权
标题翻译：使用磁性颗粒去除污染的方法和设备
公开(公告)号：US20100313907A1
公开(公告)日：2010-12-16
申请号：US12483518
申请日：2009-06-12
申请人： Nishant Sinha , Steve Kramer , Gurtej Sandhu
发明人： Nishant Sinha , Steve Kramer , Gurtej Sandhu
IPC分类号： B08B3/10 , B08B7/00
CPC分类号： H01L21/6704 , B03C1/01 , B03C2201/16 , B03C2201/20 , B08B3/10 , C11D3/1206 , C11D3/1213 , C11D7/20 , C11D17/0013 , H01L21/67028
摘要： Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from the surface of the substrate.
摘要翻译：提供了用于在半导体器件的制造中清洗衬底（例如，晶片）的方法和装置，其利用分散在基础流体内的磁性颗粒的组成以从衬底的表面去除污染物。

15. 发明授权

US08637113B2 Methods of forming a non-volatile resistive oxide memory array 有权
标题翻译：形成非易失性电阻氧化物存储器阵列的方法
公开(公告)号：US08637113B2
公开(公告)日：2014-01-28
申请号：US13354163
申请日：2012-01-19
申请人： Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
发明人： Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
IPC分类号： C23C18/00 , C23C20/00 , C23C28/00 , C23C30/00 , H01C17/06
CPC分类号： H01L27/101 , H01L21/0271 , Y10S438/947
摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.
摘要翻译：形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。含金属氧化物的材料形成在多条所述一条字线或位线中。在多个所述一条字线或位线之间提供一系列细长的沟槽。多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

16. 发明授权

US08034655B2 Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays 有权
标题翻译：非易失性电阻氧化物存储单元，非易失性电阻氧化物存储器阵列以及形成非易失性电阻氧化物存储器单元和存储器阵列的方法
公开(公告)号：US08034655B2
公开(公告)日：2011-10-11
申请号：US12099267
申请日：2008-04-08
申请人： John Smythe , Bhaskar Srinivasan , Gurtej Sandhu
发明人： John Smythe , Bhaskar Srinivasan , Gurtej Sandhu
IPC分类号： H01L21/8239
CPC分类号： H01L45/04 , G11C11/56 , G11C13/00 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.
摘要翻译：形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。绝缘材料沉积在第一电极上。在第一电极上形成绝缘材料的开口。开口包括侧壁和底座。开口侧壁和基底衬有包含少于填充开口的多电阻态金属氧化物材料的多电阻状态层。存储单元的第二导电电极形成在多个电阻状态层的横向内侧的开口的内部，该电阻层衬在侧壁上，并且在衬底基底上的多电阻状态层的顶部形成。考虑了其他方面和实现。

17. 发明授权

US07851307B2 Method of forming complex oxide nanodots for a charge trap 有权
标题翻译：形成电荷陷阱复合氧化物纳米点的方法
公开(公告)号：US07851307B2
公开(公告)日：2010-12-14
申请号：US11840485
申请日：2007-08-17
申请人： Nirmal Ramaswamy , Gurtej Sandhu , Bhaskar Srinivasan , John Smythe
发明人： Nirmal Ramaswamy , Gurtej Sandhu , Bhaskar Srinivasan , John Smythe
IPC分类号： H01L21/336
CPC分类号： H01L21/31691 , H01L21/28273 , H01L21/3142 , H01L29/42332 , H01L29/7881
摘要： Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.
摘要翻译：公开了方法和装置，例如涉及为例如可以包括闪速存储器单元的存储器件形成电荷阱的那些。将衬底暴露于钛源材料，锶源材料和能够与钛源材料和锶源材料形成氧化物的氧源材料的时间分离的脉冲，以在衬底上形成电荷捕获层。

18. 发明授权

US08772166B2 Spacer process for on pitch contacts and related structures 有权
标题翻译：间距接触和相关结构的间隔过程
公开(公告)号：US08772166B2
公开(公告)日：2014-07-08
申请号：US13526792
申请日：2012-06-19
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了包括用于增加集成电路中的隔离特征的密度的方法。还公开了相关联的结构。在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料，留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

19. 发明授权

US08211803B2 Spacer process for on pitch contacts and related structures 有权
标题翻译：间距接触和相关结构的间隔过程
公开(公告)号：US08211803B2
公开(公告)日：2012-07-03
申请号：US12781681
申请日：2010-05-17
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。还公开了与该方法相关联的结构。在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。互连可以由间距倍增形成。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。可选择定义的材料中的特征被修剪到期望的尺寸。间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料以留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

20. 发明申请

US20120122292A1 Methods of Forming a Non-Volatile Resistive Oxide Memory Array 有权
标题翻译：形成非易失性电阻氧化物存储器阵列的方法
公开(公告)号：US20120122292A1
公开(公告)日：2012-05-17
申请号：US13354163
申请日：2012-01-19
申请人： Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
发明人： Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
IPC分类号： H01L21/02
CPC分类号： H01L27/101 , H01L21/0271 , Y10S438/947
摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.
摘要翻译：形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。含金属氧化物的材料形成在多条所述一条字线或位线中。在多个所述一条字线或位线之间提供一系列细长的沟槽。多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

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