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11. 发明授权

US07474126B2 Parallel bipolar logic devices and methods for using such 有权
标题翻译：并联双极逻辑器件及其使用方法
公开(公告)号：US07474126B2
公开(公告)日：2009-01-06
申请号：US11626871
申请日：2007-01-25
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K19/20 , H03K19/086
CPC分类号： H03K19/20
摘要： Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.
摘要翻译：本文公开了各种逻辑门及其使用方法。例如，本发明的一些实施例提供并行差分逻辑门。这种逻辑门包括两个或更多个差分输入对。每个差分对中的第一晶体管的集电极都经由第一负载电阻器电耦合到上电压。类似地，每个差分对中的第二晶体管的集电极都经由第二负载电阻器电耦合到高电压。根据为第一和第二负载电阻选择的相对值，门作为“与”门或“或”门。

12. 发明申请

US20130265733A1 INTERCHIP COMMUNICATION USING AN EMBEDDED DIELECTRIC WAVEGUIDE 审中-公开
标题翻译：使用嵌入式电介质波导的交互通信
公开(公告)号：US20130265733A1
公开(公告)日：2013-10-10
申请号：US13439621
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： H05K1/11 , H05K1/18
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/16 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

13. 发明申请

US20130099824A1 REDUCED OFFSET COMPARATOR 有权
标题翻译：减少偏移比较器
公开(公告)号：US20130099824A1
公开(公告)日：2013-04-25
申请号：US13281227
申请日：2011-10-25
申请人： Robert F. Payne , Baher S. Haroun
发明人： Robert F. Payne , Baher S. Haroun
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.
摘要翻译：提供了一种装置。该装置包括后端电路和冗余输入电路对。每对冗余输入电路被配置为形成差分对晶体管，并且每个冗余输入电路包括多路复用器和一组晶体管。多路复用器耦合到后端电路，并且来自该组晶体管的每个晶体管具有第一无源电极，第二无源电极和控制电极。来自晶体管组的每个晶体管的第一无源电极耦合到多路复用器，并且来自该组晶体管的控制电极耦合在一起。

14. 发明授权

US08269661B2 Pipelined ADC having a three-level DAC elements 有权
标题翻译：流水线ADC具有三电平DAC元件
公开(公告)号：US08269661B2
公开(公告)日：2012-09-18
申请号：US12904688
申请日：2010-10-14
申请人： Marco Corsi , Robert F. Payne
发明人： Marco Corsi , Robert F. Payne
IPC分类号： H03M1/34
CPC分类号： H03M1/069 , H03M1/44
摘要： In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used.
摘要翻译：在传统的流水线模数转换器（ADC）中，通常在使用两态开关或段的ADC级中采用数模转换器（DAC）。这种安排的一个问题是，对于每个DAC状态，每个DAC开关都有来自其当前源的噪声贡献。然而，这里使用DAC，其使用三态DAC开关，其减少了DAC开关的电流源的噪声贡献，并减少了使用的面积。

15. 发明授权

US08018369B2 Error correction method and apparatus 有权
标题翻译：纠错方法及装置
公开(公告)号：US08018369B2
公开(公告)日：2011-09-13
申请号：US12896603
申请日：2010-10-01
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/38
CPC分类号： G05F3/265
摘要： A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.
摘要翻译：提供开关电流源。开关电流源通常由晶体管和电阻组成，源极具有高输出阻抗。与切换的电流源一起包括纠错晶体管和电阻器，其协作以通过偏置晶体管馈送电流以校正通常由开关电流源内的晶体管的电流增益或电流导致的误差。然而，为了实现这一点，电阻器被选择为具有足够大的值，使得来自误差校正晶体管的电流流过偏置晶体管。

16. 发明申请

US20090021283A1 HIGH SPEED LATCHED COMPARATOR 审中-公开
标题翻译：高速封锁比较器
公开(公告)号：US20090021283A1
公开(公告)日：2009-01-22
申请号：US11957640
申请日：2007-12-17
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03K5/22
CPC分类号： H03K3/356139
摘要： An improved latched comparator, including a track mode circuit, a latch and a latch and track select circuit. The track mode circuit includes two transistors having their sources connected together, and their respective gates receiving a respective first and second input, and their drains connected to the power supply by respective resistors. The latch includes a further two transistors having their sources connected together, a gate of each connected to a drain of the other, and their drains connected to a respective one of the common connection node of the first transistor and the first resistor, and the second transistor and the second resistor. The latch and track select circuit includes a further transistor having an source connected to a current sink connected to ground, having a gate connected to receive a track signal and having a drain connected to the common connection node of the first and second transistors, and a still further transistor having a source connected to the current sink connected to ground, having a gate connected to receive a latch signal and having a drain connected to the common connection node of the third and fourth transistors. Bipolar embodiments are also included.
摘要翻译：一种改进的锁存比较器，包括轨道模式电路，锁存器和锁存和轨道选择电路。轨道模式电路包括其源极连接在一起的两个晶体管，并且其各自的栅极接收相应的第一和第二输入端，并且它们的漏极通过相应的电阻器连接到电源。锁存器包括另外两个晶体管，其源极连接在一起，每个晶体管连接到另一个的漏极，并且其漏极连接到第一晶体管和第一电阻器的公共连接节点中的相应一个，晶体管和第二个电阻。锁存和轨道选择电路包括另外的晶体管，其具有连接到连接到地的电流宿的源极，具有连接到栅极的栅极，其接收轨道信号并具有连接到第一和第二晶体管的公共连接节点的漏极，以及另一个晶体管具有连接到连接到地的电流宿的源极，其具有连接的栅极，以接收锁存信号，并且具有连接到第三和第四晶体管的公共连接节点的漏极。还包括双极实施例。

17. 发明授权

US07443913B2 High speed decision feedback equalizer 有权
标题翻译：高速判决反馈均衡器
公开(公告)号：US07443913B2
公开(公告)日：2008-10-28
申请号：US10777612
申请日：2004-02-12
申请人： Bhavesh G. Bhakta , Sridhar Ramaswamy , Robert F. Payne , Song Wu
发明人： Bhavesh G. Bhakta , Sridhar Ramaswamy , Robert F. Payne , Song Wu
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.
摘要翻译：均衡器包括采样器，滤波器和夏季。采样器采样表示输入通信信号的信号，以确定具有通信设备数据速率的数字判定输出信号。滤波器从采样器接收数字判定输出信号，并从中产生均衡信号。夏天耦合到采样器和滤波器，并将输入通信信号与均衡信号组合在一起。此外，多个时钟控制与采样器相关联的定时。这些时钟具有小于数字决策输出信号的预定数据速率的频率。

18. 发明申请

US20080143411A1 Latched Comparator and Methods for Using Such 有权
标题翻译：锁定比较器及其使用方法
公开(公告)号：US20080143411A1
公开(公告)日：2008-06-19
申请号：US11626860
申请日：2007-01-25
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K3/12
CPC分类号： H03K3/2885
摘要： Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies a similar current to the latch circuit during a latch phase.
摘要翻译：本文公开了用于比较信号的各种系统和方法。例如，本发明的一些实施例为比较器电路提供前置放大器电路，锁存电路和电流重用电路。当前的再利用电路在透明相位期间向前置放大器电路施加电流，并且在锁存阶段期间向闩锁电路施加类似的电流。

19. 发明申请

US20080143388A1 Parallel Bipolar Logic Devices and Methods for Using Such 有权
标题翻译：并联双极逻辑器件及其使用方法
公开(公告)号：US20080143388A1
公开(公告)日：2008-06-19
申请号：US11626871
申请日：2007-01-25
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K19/20
CPC分类号： H03K19/20
摘要： Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.
摘要翻译：本文公开了各种逻辑门及其使用方法。例如，本发明的一些实施例提供并行差分逻辑门。这种逻辑门包括两个或更多个差分输入对。每个差分对中的第一晶体管的集电极都经由第一负载电阻器电耦合到上电压。类似地，每个差分对中的第二晶体管的集电极都经由第二负载电阻器电耦合到高电压。根据为第一和第二负载电阻选择的相对值，门作为“与”门或“或”门。

20. 发明授权

US09405064B2 Microstrip line of different widths, ground planes of different distances 有权
标题翻译：不同宽度的微带线，不同距离的接地层
公开(公告)号：US09405064B2
公开(公告)日：2016-08-02
申请号：US13439557
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： G02B6/12 , H05K1/02 , G02B6/122 , H01P3/12
CPC分类号： H05K1/0239 , G02B6/12004 , G02B6/1228 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/16 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K1/115 , H05K1/18 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

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