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    • 12. 发明授权
    • One-time UV-programmable non-volatile semiconductor memory and method of programming such a semiconductor memory
    • 一次性UV可编程非易失性半导体存储器和编程这种半导体存储器的方法
    • US06437398B2
    • 2002-08-20
    • US09846599
    • 2001-04-30
    • Franciscus Petrus Widdershoven
    • Franciscus Petrus Widdershoven
    • H01L29788
    • H01L27/11521G11C16/18H01L27/115
    • One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) formed in a surface zone (11) of a semiconductor substrate (10). Said semiconductor zones adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.
    • 一次性UV可编程只读存储器(1)包括以行和列为矩阵排列的MOS晶体管(T)形式的多个存储器单元,每个晶体管包括源极和漏极区域(12) )和形成在半导体衬底(10)的表面区(11)中的沟道区(13)。 所述半导体区域邻接在半导体衬底的表面上形成有层结构(17)的表面(14),其包括浮动栅极(16)和控制栅极(15)。 层结构设置有窗口(18),UV辐射可以通过该窗口到达浮动门的边缘。 存储器还设置有用于在通过UV辐射对存储器进行编程期间在衬底(10)和控制栅极(16)之间产生电压的装置。 因此,可以在编程期间对存储器进行编程而不需要外部接触。
    • 14. 发明申请
    • Method of Fabricating a Duel-Gate Fet
    • 制造决斗门的方法
    • US20080318375A1
    • 2008-12-25
    • US11815100
    • 2006-01-23
    • Wibo Daniel Van NoortFranciscus Petrus WiddershovenRadu Surdeanu
    • Wibo Daniel Van NoortFranciscus Petrus WiddershovenRadu Surdeanu
    • H01L21/8238
    • H01L29/785H01L29/66795H01L29/7854
    • The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.
    • 本发明提供了一种使用常规半导体处理技术制造极短的双栅极FET的方法,其具有非常小且可重现的鳍,其间距和宽度都小于可以用光刻技术获得的。 在基板(1)上的突起(2)上形成第一层(3)和第二层(4),然后露出突起(2)的上表面。 相对于突起(2)和第二层(4),第一层(3)的一部分被选择性地去除,从而形成翅片(6)和沟槽(5)。 还提出了形成多个翅片(6)和沟槽(5)的方法。 通过在沟槽(5)中形成栅电极(7)和源极和漏极区域来产生双栅极FET。 此外,提出了一种制造具有可分别偏置的两个栅电极的极短的非对称双栅极FET的方法。
    • 17. 发明授权
    • Self-aligned 2-bit “double poly CMP” flash memory cell
    • 自对准2位“双多晶CMP”闪存单元
    • US07214579B2
    • 2007-05-08
    • US10532292
    • 2002-08-18
    • Franciscus Petrus WiddershovenMichiel Jos Van Duuren
    • Franciscus Petrus WiddershovenMichiel Jos Van Duuren
    • H01L21/8239
    • G11C16/0458H01L27/115H01L27/11521
    • Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (8), a capping layer (6) and side-wall spacers (10), the cell further including source and drain contacts (22), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer (12) with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (12); defining the intermediate access gate (AG) in the planarized poly-Si layer (14) by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.
    • 存储单元的制造,该单元包括第一浮栅堆叠(A),第二浮栅堆叠(B)和中间存取栅极(AG),所述浮栅叠层(A,B)包括第一栅氧化层 4),浮动栅极(FG),控制栅极(CG; CG1,CGu),多晶硅间介电层(8),封盖层(6)和侧壁间隔物(10) 漏极触点(22),其中所述制造包括:在相同的处理步骤中限定所述浮栅堆叠以具有相同的高度; 在浮栅上沉积堆叠具有比浮栅堆叠高度更大的厚度的多晶硅层(12); 平面化多晶硅层(12); 通过在浮栅堆叠之间的多晶硅层和多晶硅蚀刻步骤之间的存取栅掩模步骤,在平坦化的多晶硅层(14)中限定中间栅极(AG)。
    • 18. 发明授权
    • Data processing device with a memory location in which data is stored according to a WOM (write once memory) code
    • 具有根据WOM(一次写入存储器)代码存储数据的存储器位置的数据处理设备
    • US07177974B2
    • 2007-02-13
    • US10755238
    • 2004-01-12
    • Sebastian EgnerFranciscus Petrus Widdershoven
    • Sebastian EgnerFranciscus Petrus Widdershoven
    • G11C17/00G11C7/10
    • G11C17/005
    • A device contains a memory that stores a WOM codeword that encodes successive generations of data values. When the codeword must be updated to represent a new data value, the device determines which updates of the dataword can be realized by feasible single bit updates to the WOM (Write Once Memory) codeword. If no feasible single bit update is possible, feasible two-bit updates are considered. Under control of the new data values a connection circuit routes feasibility signals for various updates, that signal the single-bit feasibility of the updates. Routing brings together pairs of feasibility signals for updates that together produce a WOM codeword that encodes the new data value. A pair is selected in which both feasibility signals indicate feasibility and the codeword is updated according to the updates involved in the pair. Preferably, the routing is realized with a connection circuit that comprises a number of layers of subcircuits, each routing the feasibility signals dependent on a respective bit of the new dataword. Also preferably, the WOM code is designed so that each of a number of updates to the data word can be realized by setting singles ones of a plurality of bits.
    • 设备包含存储编码连续几代数据值的WOM码字的存储器。 当代码字必须被更新以表示新的数据值时,设备通过对WOM(一次写入存储器)码字的可行单位更新来确定可以实现数据字的哪些更新。 如果没有可行的单比特更新是可行的,则考虑可行的两比特更新。 在新的数据值的控制下,一个连接电路可以路由各种更新的可行性信号,这些信号表明更新的单位可行性。 路由汇总了可用信号对,用于一起生成编码新数据值的WOM码字的更新。 选择一对,其中两个可行性信号指示可行性,并且根据该对中涉及的更新来更新码字。 优选地,路由通过包括多个子电路层的连接电路实现,每个子电路依赖于新数据字的相应位来路由可行性信号。 还优选地,WOM码被设计为使得可以通过设置多个比特的单个数目来实现数据字的多个更新中的每一个。
    • 20. 发明授权
    • Sensor and a method of assembling a sensor
    • 传感器和组装传感器的方法
    • US09375711B2
    • 2016-06-28
    • US13043352
    • 2011-03-08
    • Romano HoofmanGerard ReuversFranciscus Petrus WiddershovenEvelyne GrideletMarcus Henricus van Kleef
    • Romano HoofmanGerard ReuversFranciscus Petrus WiddershovenEvelyne GrideletMarcus Henricus van Kleef
    • G01N27/00B01L3/00G01N27/327
    • B01L3/502715B01L2200/12B01L2300/0645G01N27/3275Y10T29/49105
    • “Click-assembly” methods of assembling a sensor for sensing biologically-active molecules by measuring impedance changes, are disclosed, comprising supporting a bio-sensor on a carrier, the bio-sensor comprising an electronic component having at least one micro-electrode and at least one electrical contact, functionalizing the bio-sensor by physically or chemically coupling a bio-receptor molecule to each of the at least one micro-electrode, and subsequently assembling the bio-sensor with a micro-fluidic unit by means of a clamp which clamps the bio-sensor with the micro-fluidic unit, such that in use a fluid introduced into the micro-fluidic unit is able to contact the bio-receptor and is isolated from the electrical contact. The clamp may be a spring, and the method may avoid a requirement for sealing by chemical or thermal means and thereby avoid damaging the bio-receptor.Sensors which can be assembled according to such methods are also disclosed.
    • 公开了通过测量阻抗变化来组装用于感测生物活性分子的传感器的“点击组装”方法,其包括在载体上支撑生物传感器,所述生物传感器包括具有至少一个微电极的电子部件和 至少一个电接触,通过将所述生物受体分子物理或化学耦合至所述至少一个微电极中的每一个来官能化所述生物传感器,以及随后通过夹具将所述生物传感器与微流体单元组装 其利用微流体单元夹持生物传感器,使得在使用中,引入微流体单元的流体能够接触生物接受体并与电接触物隔离。 夹具可以是弹簧,并且该方法可以避免通过化学或热方式对密封的要求,从而避免损坏生物受体。 还公开了可以根据这些方法组装的传感器。