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11. 发明授权

US4298628A Method for manufacturing fried tofu products 失效
标题翻译：油炸豆腐制品的制造方法
公开(公告)号：US4298628A
公开(公告)日：1981-11-03
申请号：US66821
申请日：1979-08-14
申请人： Toshiyuki Nagata , Masahiko Terashima , Kazuto Mashima
发明人： Toshiyuki Nagata , Masahiko Terashima , Kazuto Mashima
IPC分类号： A23L11/00 , A23C20/02 , A23J3/16 , A23J3/00
CPC分类号： A23C20/025 , A23J3/16
摘要： A method for manufacturing a fried tofu product comprises kneading a mixture of vegetable proteinaceous material containing about 60% or more by weight based on the weight of the solids thereof with water, adding an alkaline earth metal compound as a coagulating agent in an amount of 1% or more by weight, shaping the mixture into any desired shape and deep-frying the same, thereby providing a fried tofu product.
摘要翻译：油炸豆腐制品的制造方法包括将含有约60重量％以上的固体重量的植物蛋白质混合物与水混合，加入作为凝固剂的碱土金属化合物1份％或更多的重量，将混合物成型为任何所需的形状并将其油炸，从而提供炸豆腐制品。

12. 发明授权

US07638401B2 Memory device with surface-channel peripheral transistors 有权
标题翻译：具有表面通道外围晶体管的存储器件
公开(公告)号：US07638401B2
公开(公告)日：2009-12-29
申请号：US11972048
申请日：2008-01-10
申请人： Toshiyuki Nagata
发明人： Toshiyuki Nagata
IPC分类号： H01L29/10
CPC分类号： H01L27/10894 , H01L21/823807 , H01L21/823842 , H01L21/823892 , H01L27/1052 , H01L27/10817 , H01L27/10852 , H01L27/10897
摘要： A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates 58n, while simultaneously doping a first and a second source/drain region 82 adjacent each of the first conductivity type peripheral gates 58n.
摘要翻译：一种形成包括阵列和外围电路的存储器件（例如，DRAM）的方法。形成多个未掺杂的多晶硅栅极58。这些门58分为三组; 即第一导电型外围栅极58p，第二导电型外围栅极58n和阵列栅极58a。阵列栅极58a和第一导电型外围栅极58n被掩蔽，使得第二导电型外围栅极58p保持未屏蔽。然后可以通过掺杂每个第二导电类型的外围栅极58p来形成多个第二导电类型的外围晶体管，同时掺杂与第二导电型周边栅极58p相邻的第一和第二源极/漏极区域84。然后，第二导电型外围栅极58p被掩蔽，使得第一导电类型的外围栅极58n保持未屏蔽。通过掺杂第一导电型周边栅极58n中的每一个，同时掺杂与第一导电型周边栅极58n中的每一个相邻的第一和第二源极/漏极区域82，形成多个第一导电型外围晶体管。

13. 发明授权

US6121248A Anti-viral agent 失效
标题翻译：抗病毒剂
公开(公告)号：US6121248A
公开(公告)日：2000-09-19
申请号：US146133
申请日：1998-09-02
申请人： Mineo Saneyoshi , Toshiyuki Nagata
发明人： Mineo Saneyoshi , Toshiyuki Nagata
IPC分类号： A61K31/70 , A61K31/7042 , A61K31/7052 , A61K31/7064 , A61P31/12 , C07H19/06 , A01N43/04
CPC分类号： C07H19/06 , Y02P20/55
摘要： Disclosed is an anti-viral agent against varicella-zoster virus or cytomegalovirus comprising, as an active ingredient, 2-thio-5-halogenopyrimidine arabinoside of the formula (1): ##STR1## wherein B denotes a thiopyrimidine base of the formula (2) or (3): ##STR2## where X denotes a halogen atom; or ##STR3## where X denotes a halogen atom; and wherein each of R.sup.1, R.sup.2 and R.sup.3 is a hydrogen atom or a hydroxyl protecting group.
摘要翻译：公开了一种抗水痘带状疱疹病毒或巨细胞病毒的抗病毒剂，其包含式（1）的2-硫代-5-卤代嘧啶阿拉伯糖苷作为活性成分：其中B表示式（2）的硫代嘧啶碱或（ 3）：其中X表示卤素原子; 或其中X表示卤素原子; 并且其中R 1，R 2和R 3各自为氢原子或羟基保护基。

14. 发明授权

US6028784A Ferroelectric memory device having compact memory cell array 有权
标题翻译：具有紧凑型存储单元阵列的铁电存储器件
公开(公告)号：US6028784A
公开(公告)日：2000-02-22
申请号：US300931
申请日：1999-04-28
申请人： Kazuya Mori , Toshiyuki Nagata
发明人： Kazuya Mori , Toshiyuki Nagata
IPC分类号： G11C7/18 , G11C11/22 , H01L27/115 , G11C7/00
CPC分类号： H01L27/11502 , G11C11/22 , G11C7/18
摘要： A ferroelectric random access memory (FeRAM) is disclosed. The FeRAM (400) provides a folded bit line array having memory cells (402a-402f and 404a-404d) with an area equivalent to 6F.sup.2, where F is a minimum feature size. Reduced array size is achieved by utilizing access transistors of complementary conductivity type within the array. First type memory cells (402a-402f) having n-channel access transistors (N400a-N400f), are formed next to second type memory cells (404a-404d) having p-channel access transistors (P400a-P400d). Bit lines (410a-410e) are arranged into bit line pairs, with a first bit line of each pair being coupled to first type memory cells (402a-402f) and the second bit line of each bit line pair being coupled to second type memory cells (404a-404d). When a word line is driven to a first voltage, ferroelectric capacitor data is driven on the first bit line, while the second bit line provides a reference voltage. When a word line is driven to a second voltage, ferroelectric capacitor data is driven on the second bit line and the first bit line provides a reference voltage.
摘要翻译：公开了一种铁电随机存取存储器（FeRAM）。 FeRAM（400）提供具有存储单元（402a-402f和404a-404d）的折叠位线阵列，其面积等于6F2，其中F是最小特征尺寸。通过利用阵列内的互补导电类型的存取晶体管来实现减小的阵列尺寸。在具有p沟道存取晶体管（P400a-P400d）的第二类型存储单元（404a-404d）旁边形成具有n沟道存取晶体管（N400a-N400f）的第一类型存储单元（402a-402f）。位线（410a-410e）被布置成位线对，每对的第一位线耦合到第一类型存储单元（402a-402f），并且每个位线对的第二位线被耦合到第二类型存储器细胞（404a-404d）。当字线被驱动到第一电压时，铁电电容器数据在第一位线上被驱动，而第二位线提供参考电压。当字线被驱动到第二电压时，在第二位线上驱动铁电电容器数据，并且第一位线提供参考电压。

15. 发明授权

US5563433A French-type semiconductor memory device with enhanced trench capacitor-transistor connection 失效
标题翻译：法国式半导体存储器件，具有增强的沟槽电容 - 晶体管连接
公开(公告)号：US5563433A
公开(公告)日：1996-10-08
申请号：US883502
申请日：1992-05-15
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L28/40
摘要： A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell.Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.
摘要翻译：一种具有这样的结构的半导体器件，其特征在于，预先连接到绝缘膜（54）的步骤（54a）形成导电膜（90），并且导电层（63）与上述导电膜被涂覆以形成存储单元的侧面接触。即使在导电层（63）中发生断裂的情况下，仍然通过基板导电膜（90）保持导电性，实际上不发生断线。此外，可以通过例如在不施加特殊掩模的情况下回蚀刻方法来形成上述导电层的图案; 因此，简化了制造过程。

16. 发明申请

US20140340814A1 MEMS VARIABLE CAPACITOR WITH ENHANCED RF PERFORMANCE 有权
标题翻译：具有增强射频性能的MEMS可变电容器
公开(公告)号：US20140340814A1
公开(公告)日：2014-11-20
申请号：US14240654
申请日：2012-09-04
申请人： Robertus Petrus Van Kampen , Anartz Unamuno , Richard L. Knipe , Vikram Joshi , Roberto Gaddi , Toshiyuki Nagata
发明人： Robertus Petrus Van Kampen , Anartz Unamuno , Richard L. Knipe , Vikram Joshi , Roberto Gaddi , Toshiyuki Nagata
IPC分类号： H01G5/16 , B81C1/00 , B81B3/00
CPC分类号： H01G5/16 , B81B3/0051 , B81C1/00158 , B81C1/00476 , B81C1/00523 , H01G5/18
摘要： In a MEMS device, the manner in which the membrane lands over the RF electrode can affect device performance. Bumps or stoppers placed over the RF electrode can be used to control the landing of the membrane and thus, the capacitance of the MEMS device. The shape and location of the bumps or stoppers can be tailored to ensure proper landing of the membrane, even when over-voltage is applied. Additionally, bumps or stoppers may be applied on the membrane itself to control the landing of the membrane on the roof or top electrode of the MEMS device.
摘要翻译：在MEMS器件中，膜抵住RF电极的方式可能会影响器件性能。放置在RF电极上的撞击器或塞子可用于控制膜的着陆，从而控制MEMS器件的电容。可以调整凸块或塞子的形状和位置，以确保膜的适当着陆，即使施加过电压。此外，凸块或塞子可以施加在膜本身上以控制膜在MEMS装置的顶部或顶部电极上的着陆。

17. 发明授权

US06873001B1 Reduced size plate layer improves misalignments for CUB DRAM 有权
标题翻译：减小尺寸的板层改善了CUB DRAM的未对准
公开(公告)号：US06873001B1
公开(公告)日：2005-03-29
申请号：US09332360
申请日：1999-06-10
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Masayuki Moroi , Atsushi Satoh
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Masayuki Moroi , Atsushi Satoh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10811 , H01L27/10888 , H01L28/91
摘要： In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
摘要翻译：在使用电容器下位线（CUB）布局的DRAM阵列中，电容器的平板层的面积显着减小，以减少位线与底层晶体管之间的连接中的不对准。

18. 发明授权

US06580112B2 Method for fabricating an open can-type stacked capacitor on an uneven surface 有权
标题翻译：在不平坦表面上制造开罐式叠层电容器的方法
公开(公告)号：US06580112B2
公开(公告)日：2003-06-17
申请号：US09855401
申请日：2001-05-15
申请人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku , Toshiyuki Nagata
发明人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku , Toshiyuki Nagata
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L28/92
摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).
摘要翻译：通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。形成第一电极（70,170,200）的侧壁（74,174）。电介质层（80）形成在第一电极（70,170,200）的外侧。电容器的第二电极（82）形成在电介质层（80）的外侧。

19. 发明授权

US07339220B2 Memory device with surface-channel peripheral transistors 有权
标题翻译：具有表面通道外围晶体管的存储器件
公开(公告)号：US07339220B2
公开(公告)日：2008-03-04
申请号：US10287571
申请日：2002-11-04
申请人： Toshiyuki Nagata
发明人： Toshiyuki Nagata
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/823807 , H01L21/823842 , H01L21/823892 , H01L27/1052 , H01L27/10817 , H01L27/10852 , H01L27/10897
摘要： A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates 58n, while simultaneously doping a first and a second source/drain region 82 adjacent each of the first conductivity type peripheral gates 58n.
摘要翻译：一种形成包括阵列和外围电路的存储器件（例如，DRAM）的方法。形成多个未掺杂多晶硅栅极58。这些门58分为三组; 即第一导电型外围栅极58p，第二导电型外围栅极58n和阵列栅极58a。阵列栅极58a和第一导电型外围栅极58n被掩蔽，使得第二导电型外围栅极58p保持未屏蔽。然后可以通过掺杂每个第二导电型外围栅极58 p来形成多个第二导电类型的外围晶体管，同时掺杂与第二导电型周边栅极58 p相邻的第一和第二源极/漏极区域84。然后对第二导电类型的外围栅极58 p进行掩模，使得第一导电型外围栅极58n保持未屏蔽。多个第一导电型外围晶体管通过掺杂每个第一导电类型的外围栅极58 n而形成，同时掺杂第一和第二源极/漏极区域82，其邻近于每个第一导电型周边栅极58 n。

20. 发明申请

US20050030804A1 Reduced size plate layer improves misalignments in CUB DRAM 审中-公开
标题翻译：减小尺寸的板层改善了CUB DRAM中的未对准
公开(公告)号：US20050030804A1
公开(公告)日：2005-02-10
申请号：US10936735
申请日：2004-09-07
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Masayuki Moroi , Atsushi Satoh
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Masayuki Moroi , Atsushi Satoh
IPC分类号： H01B13/00 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10811 , H01L27/10882
摘要： In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
摘要翻译：在使用电容器下位线（CUB）布局的DRAM阵列中，电容器的平板层的面积显着减小，以减少位线和底层晶体管之间的连接中的不对准。

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