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11. 发明申请

US20070288769A1 METHOD FOR INCREASING THE DATA PROCESSING CAPABILITY OF A COMPUTER SYSTEM 有权
标题翻译：提高计算机系统数据处理能力的方法
公开(公告)号：US20070288769A1
公开(公告)日：2007-12-13
申请号：US11423718
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/172
摘要： A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.
摘要翻译：提供了一种用于动态提高计算机系统的数据处理能力的方法。计算机系统包括处理器，存储器和芯片组。计算机系统的数据处理能力被分为预定数量的性能增强模式。检查至少一个性能增强模式转换条件以确定是否自动提高计算机系统的性能增强模式。处理器在计算机系统的性能提升模式转换期间被暂停使用处理器总线。通过增加处理器的第一工作频率，处理器总线的第二工作频率和存储器的第三工作频率来提高计算机系统的性能增强模式。当计算机系统的性能提升模式进一步提高时，计算机系统的数据处理速度进一步提高。

12. 发明申请

US20050263849A1 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 审中-公开
标题翻译：用于向主桥芯片基板和主板提供稳定电源的布局结构
公开(公告)号：US20050263849A1
公开(公告)日：2005-12-01
申请号：US11196039
申请日：2005-08-02
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.
摘要翻译：本发明涉及一种用于向四层母板和主桥芯片基板提供稳定电源的布局结构。在本发明中，在用于布局主桥芯片和功率环的底部焊料层的顶部信号层和功率路径上，去耦电容器连接在接地焊盘/焊球和电源接合焊盘/ 焊球的动力路径和动力环，从而为主桥芯片的运行提供稳定的电源。在本发明中，与每个电源焊盘/焊球相连的接地焊盘/焊球可以是与功率焊盘/焊球最接近的接地焊盘/焊球。此外，在主桥芯片基板的实施例中，去耦电容器可以设置在电源环的四个角落或者接合线下方，或者可以封装在模制化合物内部。

13. 发明授权

US06836848B2 Power management integrated circuit for overriding an internal frequency ID code of a processor and for providing frequency ID value to a bridge chipset 有权
标题翻译：电源管理集成电路，用于覆盖处理器的内部频率ID码，并为桥接芯片组提供频率ID值
公开(公告)号：US06836848B2
公开(公告)日：2004-12-28
申请号：US09683243
申请日：2001-12-05
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： G06F126
CPC分类号： G06F1/26
摘要： An integrated circuit includes voltage identification (VID) logic and frequency identification logic (FID) for a CPU, as well as power good circuitry for indicating the suitability of electrical power supplies. A VID output signal to control a core voltage provided to the CPU is generated according to an input VID signal provided by the CPU, a sleep state signal, and a CPU mobility-type signal. FID, VID and power detection logic all level shift signals as required for external devices. A programmable table enables overriding of output FID and VID values.
摘要翻译：集成电路包括用于CPU的电压识别（VID）逻辑和频率识别逻辑（FID），以及用于指示电力供应适用性的电力良好电路。根据由CPU提供的输入VID信号，休眠状态信号和CPU移动性型信号，生成用于控制提供给CPU的核心电压的VID输出信号。 FID，VID和功率检测逻辑根据外部设备所需的所有电平移位信号。可编程表可以覆盖输出FID和VID值。

14. 发明授权

US07689847B2 Method for increasing the data processing capability of a computer system 有权
标题翻译：提高计算机系统数据处理能力的方法
公开(公告)号：US07689847B2
公开(公告)日：2010-03-30
申请号：US11423718
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/172
摘要： A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.
摘要翻译：提供了一种用于动态提高计算机系统的数据处理能力的方法。计算机系统包括处理器，存储器和芯片组。计算机系统的数据处理能力被分为预定数量的性能增强模式。检查至少一个性能增强模式转换条件以确定是否自动提高计算机系统的性能增强模式。处理器在计算机系统的性能提升模式转换期间被暂停使用处理器总线。通过增加处理器的第一工作频率，处理器总线的第二工作频率和存储器的第三工作频率来提高计算机系统的性能增强模式。当计算机系统的性能提升模式进一步提高时，计算机系统的数据处理速度进一步提高。

15. 发明申请

US20060203740A1 METHOD AND RELATED APPARATUS FOR MONITORING SYSTEM BUS 审中-公开
标题翻译：用于监控系统总线的方法和相关装置
公开(公告)号：US20060203740A1
公开(公告)日：2006-09-14
申请号：US11162608
申请日：2005-09-16
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： H04L1/00
CPC分类号： G06F11/0745 , G06F11/0757 , G06F11/3471 , G06F11/349 , G06F2201/81 , G06F2201/88
摘要： Method and related apparatus for monitoring access modules, like memory or input/output modules, linked with a system bus of a computer system. In the present invention, access modules to be monitored and their corresponding monitoring intervals are preset. When a given access module initiates information exchange via the system bus, it is checked to see if the given access module matches any of the access modules to be monitored. If a match is found, a countdown is started from the corresponding monitoring interval. If the given access module completes the information exchange before the countdown finishes, the given access module is determined to be normal. Otherwise, a predetermined timeout event is executed for responding to a potential problem of the given access module.
摘要翻译：用于监视与计算机系统的系统总线链接的访问模块（如存储器或输入/输出模块）的方法和相关装置。在本发明中，预先设定要监视的访问模块及其对应的监视间隔。当给定的访问模块通过系统总线发起信息交换时，检查给定的访问模块是否匹配要监视的任何访问模块。如果找到匹配，则从相应的监视间隔开始倒计时。如果给定的访问模块在倒计时完成之前完成信息交换，则给定的访问模块被确定为正常。否则，执行预定的超时事件以响应给定访问模块的潜在问题。

16. 发明授权

US07007175B2 Motherboard with reduced power consumption 有权
公开(公告)号：US07007175B2
公开(公告)日：2006-02-28
申请号：US10005627
申请日：2001-12-04
申请人： Nai-Shung Chang , Chia-Hsing Yu , Chia-Hsin Chen
发明人： Nai-Shung Chang , Chia-Hsing Yu , Chia-Hsin Chen
IPC分类号： G06F1/26
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/14 , Y02D50/20
摘要： A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.

17. 发明授权

US06681286B2 Control chipset having dual-definition pins for reducing circuit layout of memory slot 有权
标题翻译：具有双重定位引脚的控制芯片组，用于减少存储器插槽的电路布局
公开(公告)号：US06681286B2
公开(公告)日：2004-01-20
申请号：US09756324
申请日：2001-01-08
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1300
CPC分类号： G11C5/06 , G06F1/26 , G11C5/04 , G11C8/06 , G11C8/12 , H05K1/0246 , H05K1/0262 , H05K1/14 , H05K1/141 , H05K2201/044 , H05K2201/10022 , H05K2201/10159
摘要： A control chipset having dual-definition data pins capable of reducing circuit layout to memory module slots. Using dual-definition data pins of the control chipset and multiplexing/de-multiplexing devices, the control chipset is able to sense the particular type of memory modules plugged into memory slots automatically and hence assigning the function to each data pin accordingly. Consequently, circuit layout from the control chipset to the data pins of far off memory slots is simplified and overall circuit length is greatly reduced.
摘要翻译：具有能够将电路布局降低到存储器模块时隙的双精度数据引脚的控制芯片组。使用控制芯片组和复用/解复用器件的双重定义数据引脚，控制芯片组能够自动检测插入存储器插槽的特定类型的存储器模块，从而相应地将功能分配给每个数据引脚。因此，简化了从控制芯片组到远离存储器插槽的数据引脚的电路布局，并大大减少了整体电路长度。

18. 发明授权

US06556051B2 Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module 有权
公开(公告)号：US06556051B2
公开(公告)日：2003-04-29
申请号：US09930797
申请日：2001-08-14
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： H03B2100
CPC分类号： G11C7/1066 , G11C5/04 , G11C7/1072 , G11C11/4093
摘要： An apparatus for providing both supports including synchronous dynamic random access memory module and the double data rate dynamic random access memory module is provided. A motherboard can support standard synchronous dynamic random access memory and dual data rate dynamic random access memory by using the disable and enable functions of the terminator. The invention reduces manufacturing production waste due to complex fabrication process of memory module. In addition, the trouble of upgrading the computer by consumer can be eliminated.

19. 发明授权

US07723843B2 Multi-package module and electronic device using the same 有权
标题翻译：多包装模块和使用电子装置的电子装置
公开(公告)号：US07723843B2
公开(公告)日：2010-05-25
申请号：US12354152
申请日：2009-01-15
申请人： Chih-Hsiung Lin , Nai-Shung Chang
发明人： Chih-Hsiung Lin , Nai-Shung Chang
IPC分类号： H01L23/34
CPC分类号： H01L23/367 , H01L23/3677 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15311 , H01L2924/15321
摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.
摘要翻译：一种用于多封装模块的封装衬底。封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。还公开了一种具有封装基板的电子器件。

20. 发明授权

US07525182B2 Multi-package module and electronic device using the same 有权
标题翻译：多包装模块和使用电子装置的电子装置
公开(公告)号：US07525182B2
公开(公告)日：2009-04-28
申请号：US11243121
申请日：2005-10-04
申请人： Chih-Hsiung Lin , Nai-Shung Chang
发明人： Chih-Hsiung Lin , Nai-Shung Chang
IPC分类号： H01L23/495
CPC分类号： H01L23/367 , H01L23/3677 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15311 , H01L2924/15321
摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.
摘要翻译：一种用于多封装模块的封装衬底。封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。还公开了一种具有封装基板的电子器件。

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