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11. 发明申请

US20090065955A1 METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING 有权
标题翻译：用于加速软错误测试的方法和结构
公开(公告)号：US20090065955A1
公开(公告)日：2009-03-12
申请号：US11852353
申请日：2007-09-10
申请人： Michael S. Gordon , Kenneth P. Rodbell , Henry H. K. Tang
发明人： Michael S. Gordon , Kenneth P. Rodbell , Henry H. K. Tang
IPC分类号： H01L23/48 , G01R31/26 , H01L21/4763
CPC分类号： G01R31/2881 , G01R31/2858 , G01R31/31816 , H01L21/76825 , H01L21/84 , H01L23/53233 , H01L23/53238 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.
摘要翻译：一种集成电路，形成集成电路的方法以及用于软错误的集成电路测试的方法失败。集成电路包括：硅衬底; 形成在所述基板上的电介质层; 形成在电介质层中的导电线，将形成在基板中的半导体器件互连成电路的导线; 以及靠近一个或多个半导体器件的集成电路芯片中的α粒子发射区域。该方法包括将集成电路暴露于热中子的人造通量，以使α粒子发射区中的原子裂变为α粒子和其它原子。

12. 发明申请

US20080299720A1 STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION 审中-公开
标题翻译：使用硅氧烷之前的离子沉积的CMOS器件中的Ni单晶硅薄膜的稳定性
公开(公告)号：US20080299720A1
公开(公告)日：2008-12-04
申请号：US12124275
申请日：2008-05-21
申请人： Roy A. Carruthers , Cedrik Y. Coia , Christophe Detavernier , Christian Lavoie , Kenneth P. Rodbell
发明人： Roy A. Carruthers , Cedrik Y. Coia , Christophe Detavernier , Christian Lavoie , Kenneth P. Rodbell
IPC分类号： H01L21/8238 , H01L21/4763
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.
摘要翻译：提供了一种用于形成稳定的金属硅化物膜的方法，例如接触（源极/漏极或栅极），其在随后的热处理期间基本上不附聚。在本发明中，在形成金属硅化物之前，将能够附着到含Si层内的缺陷的离子注入到含Si层中。植入的离子稳定膜，因为发现植入物基本上防止结块或至少延迟聚集到比没有使用植入物的情况下更高的温度。

13. 发明申请

US20080211100A1 METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION 有权
标题翻译：减少硅化物接触和金属化之间的接触电阻的方法和结构
公开(公告)号：US20080211100A1
公开(公告)日：2008-09-04
申请号：US12122984
申请日：2008-05-19
申请人： Christian Lavoie , Conal E. Murray , Kenneth P. Rodbell
发明人： Christian Lavoie , Conal E. Murray , Kenneth P. Rodbell
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/485 , H01L21/28518 , H01L21/76877 , H01L21/76883 , H01L23/53209 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy).
摘要翻译：提供了其中接触开口中的接触电阻降低的半导体结构及其形成方法。这在本发明中通过用含金属锗化物的接触材料代替常规的接触冶金例如钨或金属硅化物，例如硅化镍或硅化铜，来实现。在本申请中使用的术语“含金属锗”表示纯金属锗（即MGe合金）或包含Si（即，MSiGe合金）的金属锗化物。

14. 发明申请

US20080163137A1 METHOD OF DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE 有权
标题翻译：确定设计结构的停留力与移动颗粒相关的方法
公开(公告)号：US20080163137A1
公开(公告)日：2008-07-03
申请号：US11618993
申请日：2007-01-02
申请人： Giovanni Fiorenza , Conal E. Murray , Kenneth P. Rodbell , Henry Tang
发明人： Giovanni Fiorenza , Conal E. Murray , Kenneth P. Rodbell , Henry Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/16
摘要： A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N interconnect layers into multiple pixels, and (iii) determining a first path of the traveling particle in a first interconnect layer of the N interconnect layers, (iv) identifying M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle, M being a positive integer, and (v) determining a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels.
摘要翻译：确定设计结构相对于行进颗粒的停止力的方法。该方法包括（i）提供设计结构的设计信息，该设计结构包括后端行层，其包括N个互连层，N为正整数，（ii）将N个互连层的每个互连层划分成多个像素，和（iii）确定所述N个互连层的第一互连层中的所述行进粒子的第一路径，（iv）识别所述行进粒子的所述第一路径上的所述第一互连层的所述多个像素的M个路径像素，M 作为正整数，以及（v）确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。

15. 发明授权

US07381635B2 Method and structure for reduction of soft error rates in integrated circuits 有权
标题翻译：降低集成电路中软错误率的方法和结构
公开(公告)号：US07381635B2
公开(公告)日：2008-06-03
申请号：US11183647
申请日：2005-07-18
申请人： Cyril Cabral, Jr. , Michael S. Gordon , Kenneth P. Rodbell
发明人： Cyril Cabral, Jr. , Michael S. Gordon , Kenneth P. Rodbell
IPC分类号： H01L21/44
CPC分类号： H01L23/556 , H01L21/76801 , H01L21/76834 , H01L21/76838 , H01L23/5329 , H01L23/53295 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05554 , H01L2224/05572 , H01L2224/05599 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/451 , H01L2224/48227 , H01L2224/48465 , H01L2224/85399 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01055 , H01L2924/01057 , H01L2924/01063 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/01092 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2224/05552
摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.
摘要翻译：降低集成电路中软错误率的结构和方法。该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

16. 发明授权

US06979393B2 Method for plating copper conductors and devices formed 失效
标题翻译：电镀铜导体和器件的方法
公开(公告)号：US06979393B2
公开(公告)日：2005-12-27
申请号：US10055134
申请日：2002-01-22
申请人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
发明人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
IPC分类号： C25D3/38 , C25D5/00 , C25D5/10 , C25D7/12 , H05K3/42 , C25D5/02
CPC分类号： C25D5/10 , C25D3/38 , C25D5/00 , C25D7/123 , C25D21/02 , H05K3/423
摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.
摘要翻译：公开了一种在电子基板上镀铜导体的方法和形成的器件。在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如具有大于1/3或高达1的直径/深度的纵横比的双镶嵌结构中的通孔 / 10。各种电镀参数用于在单步沉积或双步沉积过程中提供短电阻瞬变。这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

17. 发明授权

US06685548B2 Grooved polishing pads and methods of use 有权
标题翻译：凹槽抛光垫和使用方法
公开(公告)号：US06685548B2
公开(公告)日：2004-02-03
申请号：US10424840
申请日：2003-04-29
申请人： Shyng-Tsong Chen , Kenneth M. Davis , Kenneth P. Rodbell
发明人： Shyng-Tsong Chen , Kenneth M. Davis , Kenneth P. Rodbell
IPC分类号： B24B722
CPC分类号： B24B37/26 , B24D18/00
摘要： Grooves are formed in a CMP pad by positioning the pad on a supporting surface with a working surface of the pad in spaced relation opposite to a router bit and at least one projecting stop member adjacent to the router bit, an outer end portion of the bit projecting beyond the stop. When the bit is rotated, relative axial movement between the bit and the pad causes the outer end portion of the bit to cut an initial recess in the pad. Relative lateral movement between the rotating bit and the pad then forms a groove which extends laterally away from the recess and has a depth substantially the same as that of the recess. The depths of the initial recess and the groove are limited by applying a vacuum to the working surface of the pad to keep it in contact with the stop member(s). Different lateral movements between the bit and the pad are used to form a variety of groove patterns, the depths of which are precisely controlled by the stop member(s). The grooves may be formed in the polishing surface and/or the rear opposite surface of the pad and passages may be provided for interconnecting the rear grooves with the polishing surface or the front grooves.
摘要翻译：通过将衬垫定位在支撑表面上，使衬垫的工作表面与路由器刀片相对的间隔开的关系形成凹槽，并且至少一个与路由器刀头相邻的突出止动件，钻头的外端部分突出超出停止。当钻头旋转时，钻头和钻头之间的相对轴向运动使钻头的外端部分切割焊盘中的初始凹陷。旋转钻头和垫之间的相对横向运动形成一个横向延伸离开凹槽并具有与凹槽基本相同的深度的凹槽。通过将真空施加到垫的工作表面以使其与止动构件接触来限制初始凹部和凹槽的深度。钻头和垫之间的不同横向运动用于形成各种凹槽图案，其深度由止动件精确地控制。凹槽可以形成在抛光表面中和/或垫的后相对表面，并且可以设置通道用于将后槽与抛光表面或前槽相互连接。

18. 发明授权

US5912506A Multi-layer metal sandwich with taper and reduced etch bias and method for forming same 失效
标题翻译：具有锥形和减少的蚀刻偏压的多层金属夹层及其形成方法
公开(公告)号：US5912506A
公开(公告)日：1999-06-15
申请号：US937349
申请日：1997-09-20
申请人： Evan G. Colgan , Peter M. Fryer , James McKell Edwin Harper , Kenneth P. Rodbell
发明人： Evan G. Colgan , Peter M. Fryer , James McKell Edwin Harper , Kenneth P. Rodbell
IPC分类号： G02F1/1362 , H01L23/498 , H01L23/538 , H01L23/48
CPC分类号： H01L23/538 , H01L23/49866 , G02F2001/13629 , H01L2924/0002
摘要： A multi-layer metal sandwich structure with taper and reduced etch bias formed on a substrate includes a first metal layer formed on the substrate and a second metal layer formed on the first metal layer. The width of the first metal layer is greater than the width of the second metal layer at the interface of the first metal layer and the second metal layer. The second metal layer has tapered side walls. The taper angle between each side wall and the intersection of the first and second metal layers is between 5.degree. and 90.degree.. The multi-layer metal sandwich may also include a third metal layer formed on the second metal layer.
摘要翻译：在衬底上形成具有锥形和减少的蚀刻偏压的多层金属夹层结构包括形成在衬底上的第一金属层和形成在第一金属层上的第二金属层。第一金属层的宽度大于第一金属层和第二金属层的界面处的第二金属层的宽度。第二金属层具有锥形侧壁。每个侧壁与第一和第二金属层的交点之间的锥角在5°和90°之间。多层金属夹层物还可以包括形成在第二金属层上的第三金属层。

19. 发明授权

US5171642A Multilayered intermetallic connection for semiconductor devices 失效
标题翻译：用于半导体器件的多层金属间连接
公开(公告)号：US5171642A
公开(公告)日：1992-12-15
申请号：US638888
申请日：1991-01-08
申请人： Patrick W. DeHaven , J. Daniel Mis , Kenneth P. Rodbell , Paul A. Totta , James F. White
发明人： Patrick W. DeHaven , J. Daniel Mis , Kenneth P. Rodbell , Paul A. Totta , James F. White
IPC分类号： H01L21/48 , H01L23/498 , H05K1/09 , H05K3/16 , H05K3/38
CPC分类号： H01L21/4846 , H01L23/49866 , H01L2924/0002 , H05K1/09 , H05K3/16 , H05K3/388 , Y10T428/12528 , Y10T428/12743
摘要： A low copper concentration multilayered, device interconnect metallurgy, comprises an aluminum-copper (
摘要翻译：低铜浓度多层器件互连冶金包括铝 - 铜（<2重量％铜）导体，其在其一个表面上形成由IVA金属形成的金属间化合物层和来自铝 - 铜导体的铝。金属间化合物形成为仅含有金属间化合物的单相化合物。

20. 发明授权

US08492897B2 Microstructure modification in copper interconnect structures 有权
标题翻译：铜互连结构中的微结构改性
公开(公告)号：US08492897B2
公开(公告)日：2013-07-23
申请号：US13232085
申请日：2011-09-14
申请人： Cyril Cabral, Jr. , Jeffrey P. Gambino , Qiang Huang , Takeshi Nogami , Kenneth P. Rodbell
发明人： Cyril Cabral, Jr. , Jeffrey P. Gambino , Qiang Huang , Takeshi Nogami , Kenneth P. Rodbell
IPC分类号： H01L23/48
CPC分类号： H01L21/7684 , H01L21/2885 , H01L21/76841 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53238 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.
摘要翻译：金属互连结构和金属互连结构的制造方法。锰（Mn）被掺入到铜（Cu）互连结构中，以便在90nm以下的技术中改变微观结构以实现竹型晶界。优选地，竹颗粒在小于“漂白”长度的距离处分离，以便避免通过晶界的铜（Cu）扩散。添加的Mn还触发Cu颗粒向金属线底部的生长，从而形成达到底面的真正的竹结构，消除沿着金属线长度取向的晶界的Cu扩散机理。

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