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11. 发明授权

US07348653B2 Resistive memory cell, method for forming the same and resistive memory array using the same 有权
标题翻译：电阻式存储单元，其形成方法和使用其的电阻式存储器阵列
公开(公告)号：US07348653B2
公开(公告)日：2008-03-25
申请号：US11279640
申请日：2006-04-13
申请人： Byeong-Ok Cho , Moon-Sook Lee , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Takahiro Yasue
IPC分类号： H01L27/01
CPC分类号： H01L51/0001 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C13/04 , H01L27/283 , H01L51/0018 , H01L51/0591
摘要： A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.
摘要翻译：电阻式存储单元采用可光成像的可切换材料，其可以通过光化辐射进行图案化，并且在可区分的电阻状态之间可逆地切换为存储元件。因此，可光成像的可切换材料通过光化辐射直接图案化，使得可以通过简单的工艺制造电阻式存储单元，并避免灰化和剥离步骤。

12. 发明申请

US20070278482A1 Organic memory devices including organic material and fullerene layers and related methods 失效
标题翻译：包括有机材料和富勒烯层在内的有机记忆装置及相关方法
公开(公告)号：US20070278482A1
公开(公告)日：2007-12-06
申请号：US11726888
申请日：2007-03-23
申请人： Byeong-Ok Cho , Moon-Sook Lee , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Takahiro Yasue
IPC分类号： H01L29/08
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C2211/5614 , G11C2213/72 , G11C2213/77 , H01L51/0026 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0039 , H01L51/0042 , H01L51/0046
摘要： An organic memory device may include a stack of an organic material layer and a fullerene layer to provide a data storage element between first and second electrodes. The data storage element may include an organic material layer formed on the first electrode, and a fullerene layer between the organic material layer and the second electrode. Methods of fabricating organic memory devices are also discussed.
摘要翻译：有机存储器件可以包括有机材料层和富勒烯层的叠层，以在第一和第二电极之间提供数据存储元件。数据存储元件可以包括形成在第一电极上的有机材料层和有机材料层和第二电极之间的富勒烯层。还讨论了制造有机存储器件的方法。

13. 发明申请

US20110263081A1 METHODS OF MANUFACTURING CMOS TRANSISTOR 有权
标题翻译：制造CMOS晶体管的方法
公开(公告)号：US20110263081A1
公开(公告)日：2011-10-27
申请号：US13173670
申请日：2011-06-30
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/124 , B82Y10/00 , H01L27/095 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/0665 , H01L29/0673 , H01L29/45 , H01L29/7839 , H01L29/78681 , H01L29/7869
摘要： A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively.
摘要翻译：可以通过在衬底上形成第一和第二栅电极并在第一和第二栅电极上形成栅极绝缘层来提供制造CMOS晶体管的方法。可以在栅极绝缘层上形成具有第一导电类型的半导体沟道材料。可以在半导体沟道材料上形成一对欧姆接触，使得欧姆接触分别跨过第一栅电极的两侧部分。可以在半导体沟道材料上形成一对肖特基触点，使得肖特基触点分别跨过第二栅电极的两侧部分。

14. 发明申请

US20090258443A1 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090258443A1
公开(公告)日：2009-10-15
申请号：US12381987
申请日：2009-03-18
申请人： Yasue Takahiro , Byeong-Ok Cho , Moon-Sook Lee
发明人： Yasue Takahiro , Byeong-Ok Cho , Moon-Sook Lee
IPC分类号： H01L21/02
CPC分类号： H01L27/11507 , B82Y10/00 , H01L21/28291 , H01L27/101 , H01L27/285 , H01L28/40 , H01L51/0004
摘要： Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.
摘要翻译：提供非易失性存储器件及其制造方法。在一些实施例中，非易失性存储器件包括形成在衬底的上部或内部的下导电构件，形成在下导电构件上的铁电有机层，形成在铁电有机层上的保护层和上导电构件形成在保护层上以穿过下导电构件。

15. 发明授权

US08586427B2 Thin film transistors and methods of manufacturing thin film transistors 有权
标题翻译：薄膜晶体管和制造薄膜晶体管的方法
公开(公告)号：US08586427B2
公开(公告)日：2013-11-19
申请号：US13204785
申请日：2011-08-08
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L21/8234 , H01L29/786
CPC分类号： H01L29/41733 , H01L27/1292 , H01L29/42384
摘要： A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.
摘要翻译：薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。源极线可以部分地与栅电极重叠，使得与栅极重叠的源极线的两侧可以完全位于栅电极的两侧之间。漏极线可以与沟道层接触并且可以与源极线隔开通道长度。漏极线可以具有与源极线对称的结构。可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

16. 发明授权

US07994581B2 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US07994581B2
公开(公告)日：2011-08-09
申请号：US12506656
申请日：2009-07-21
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L27/092
CPC分类号： H01L27/124 , B82Y10/00 , H01L27/095 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/0665 , H01L29/0673 , H01L29/45 , H01L29/7839 , H01L29/78681 , H01L29/7869
摘要： In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively.
摘要翻译：在互补金属氧化物半导体（CMOS）晶体管及其制造方法中，在基板上设置具有第一导电类型的半导体沟道材料。具有第一导电类型的第一晶体管和具有第二导电类型的第二晶体管分别位于衬底上。第一晶体管包括位于通道材料的第一表面上的第一栅极，该第一栅极通过栅极绝缘层的介质和位于沟道材料的第二表面上的一对欧姆触点，并且跨越第一栅电极的两侧部分，分别。第二晶体管包括通过栅极绝缘层的介质定位在沟道材料的第一表面上的第二栅极和位于沟道材料的第二表面上并与第二栅电极的两侧部分交叉的一对肖特基触点，分别。

17. 发明申请

US20100013018A1 CMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20100013018A1
公开(公告)日：2010-01-21
申请号：US12506656
申请日：2009-07-21
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L27/092
CPC分类号： H01L27/124 , B82Y10/00 , H01L27/095 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/0665 , H01L29/0673 , H01L29/45 , H01L29/7839 , H01L29/78681 , H01L29/7869
摘要： In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively.
摘要翻译：在互补金属氧化物半导体（CMOS）晶体管及其制造方法中，在基板上设置具有第一导电类型的半导体沟道材料。具有第一导电类型的第一晶体管和具有第二导电类型的第二晶体管分别位于衬底上。第一晶体管包括位于通道材料的第一表面上的第一栅极，该第一栅极通过栅极绝缘层的介质和位于沟道材料的第二表面上的一对欧姆触点，并且跨越第一栅电极的两侧部分，分别。第二晶体管包括通过栅极绝缘层的介质定位在沟道材料的第一表面上的第二栅极和位于沟道材料的第二表面上并与第二栅电极的两侧部分交叉的一对肖特基触点，分别。

18. 发明申请

US20100006849A1 Thin Film Transistors 有权
标题翻译：薄膜晶体管
公开(公告)号：US20100006849A1
公开(公告)日：2010-01-14
申请号：US12497852
申请日：2009-07-06
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L27/1292 , H01L29/42384
摘要： A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.
摘要翻译：薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。漏极线可以与沟道层接触并且可以与源极线隔开通道长度。漏极线可以具有与源极线对称的结构。可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

19. 发明授权

US08022410B2 Thin film transistors 有权
标题翻译：薄膜晶体管
公开(公告)号：US08022410B2
公开(公告)日：2011-09-20
申请号：US12497852
申请日：2009-07-06
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L27/1292 , H01L29/42384
摘要： A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.
摘要翻译：薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。漏极线可以与沟道层接触并且可以与源极线隔开通道长度。漏极线可以具有与源极线对称的结构。可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

20. 发明授权

US08227303B2 Methods of manufacturing CMOS transistor 有权
标题翻译：制造CMOS晶体管的方法
公开(公告)号：US08227303B2
公开(公告)日：2012-07-24
申请号：US13173670
申请日：2011-06-30
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/124 , B82Y10/00 , H01L27/095 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/0665 , H01L29/0673 , H01L29/45 , H01L29/7839 , H01L29/78681 , H01L29/7869
摘要： A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively.
摘要翻译：可以通过在衬底上形成第一和第二栅电极并在第一和第二栅电极上形成栅极绝缘层来提供制造CMOS晶体管的方法。可以在栅极绝缘层上形成具有第一导电类型的半导体沟道材料。可以在半导体沟道材料上形成一对欧姆接触，使得欧姆接触分别跨过第一栅电极的两侧部分。可以在半导体沟道材料上形成一对肖特基触点，使得肖特基触点分别跨过第二栅电极的两侧部分。

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