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11. 发明授权

US5640051A Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex 失效
标题翻译：芯片封装，芯片载体，电路基板的端子电极和芯片封装的复合体
公开(公告)号：US5640051A
公开(公告)日：1997-06-17
申请号：US353438
申请日：1994-12-09
申请人： Yoshihiro Tomura , Yoshihiro Bessho , Yasuhiko Hakotani
发明人： Yoshihiro Tomura , Yoshihiro Bessho , Yasuhiko Hakotani
IPC分类号： H01L21/48 , H01L21/56 , H01L23/485 , H01L23/498 , H05K1/18 , H05K3/24 , H05K3/32 , H05K3/40 , H01L23/02 , H01L23/12 , H01L23/50
CPC分类号： H05K3/4007 , H01L21/4853 , H01L21/563 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L24/13 , H05K3/321 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H05K1/181 , H05K2201/0347 , H05K2201/0367 , H05K2201/09036 , H05K2201/09472 , H05K2201/09845 , H05K2201/10568 , H05K2201/10719 , H05K2201/10984 , H05K2203/0577 , H05K2203/167 , H05K3/243
摘要： A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.
摘要翻译：根据本发明的芯片载体包括：载体，其包括上表面，下表面和内导体; 以及形成在所述载体主体的上表面上的多个端子电极，所述多个端子电极将LSI芯片电连接到所述内部导体。多个用于将电路基板上的多个电极电连接到内部导体的凹部设置在载体主体的下表面上，凹部电连接到内部导体。

12. 发明授权

US5628919A Methods for producing a chip carrier and terminal electrode for a circuit substrate 失效
标题翻译：用于制造用于电路基板的芯片载体和端子电极的方法
公开(公告)号：US5628919A
公开(公告)日：1997-05-13
申请号：US439980
申请日：1995-05-12
申请人： Yoshihiro Tomura , Yoshihiro Bessho , Yasuhiko Hakotani
发明人： Yoshihiro Tomura , Yoshihiro Bessho , Yasuhiko Hakotani
IPC分类号： H01L21/48 , H01L21/56 , H01L23/485 , H01L23/498 , H05K1/18 , H05K3/24 , H05K3/32 , H05K3/40 , B44C1/22
CPC分类号： H05K3/4007 , H01L21/4853 , H01L21/563 , H01L23/49816 , H01L23/49827 , H01L24/11 , H01L24/13 , H05K3/321 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H05K1/181 , H05K2201/0347 , H05K2201/0367 , H05K2201/09036 , H05K2201/09472 , H05K2201/09845 , H05K2201/10568 , H05K2201/10719 , H05K2201/10984 , H05K2203/0577 , H05K2203/167 , H05K3/243
摘要： A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.
摘要翻译：根据本发明的芯片载体包括：载体，其包括上表面，下表面和内导体; 以及形成在所述载体主体的上表面上的多个端子电极，所述多个端子电极将LSI芯片电连接到所述内部导体。多个用于将电路基板上的多个电极电连接到内部导体的凹部设置在载体主体的下表面上，凹部电连接到内部导体。

13. 发明授权

US5004715A Dielectric ceramic composition and a multilayer ceramic capacitor and a method of manufacturing a multilayer ceramic capacitor 失效
标题翻译：介电陶瓷组合物和多层陶瓷电容器以及制造多层陶瓷电容器的方法
公开(公告)号：US5004715A
公开(公告)日：1991-04-02
申请号：US483462
申请日：1990-02-22
申请人： Yasuhiko Hakotani , Seiichi Nakatani , Satoru Yuuhaku , Tsutomu Nishimura , Toru Ishida
发明人： Yasuhiko Hakotani , Seiichi Nakatani , Satoru Yuuhaku , Tsutomu Nishimura , Toru Ishida
IPC分类号： C04B35/00 , C04B35/497 , C04B35/499 , H01B3/12 , H01G4/008 , H01G4/12
CPC分类号： H01G4/0085 , C04B35/497 , C04B35/499 , H01G4/1254
摘要： A low temperature sintering dielectric ceramic composition, which exhibits high dielectric constant, low dielectric loss, high electrical resistivity, high mechanical strength and narrow grain size distribution, is disclosed. The ceramic composition is a binary system comprising lead magnesium niobate (Pb(Mg.sub.1/3 Nb.sub.2/3)O.sub.3) and copper oxide, or a ternary system comprising lead magnesium niobate (Pb(Mg.sub.1/3 Nb.sub.2/3)O.sub.3), lead titanate (PbTiO.sub.3) and copper oxide. A multilayer ceramic capacitor comprising internal copper electrodes and ceramic dielectric layers consisting of the dielectric ceramic composition is also disclosed. A method of readily manufacturing the multilayer ceramic capacitor with copper internal electrodes is also disclosed.This fabrication method comprises a stop of forming a multilayer laminate by the green tape multilayer laminating method using dielectric ceramic tapes and a conductor paste containing CuO as its main component; a step of heat-treatment for decomposing and removing organic binder in air (binder removing process); a step of reducing CuO in the internal electrode layers to copper by heat-treatment in a mixed gas atmosphere of nitrogen and hydrogen (reduction process); and a step of sintering the multilayer laminate in a nitrogen atmosphere (sintering process).
摘要翻译：公开了一种具有高介电常数，低介电损耗，高电阻率，高机械强度和窄晶粒尺寸分布的低温烧结介电陶瓷组合物。陶瓷组合物是包含铌酸铅镁（Pb（Mg1 / 3Nb2 / 3）O3）和氧化铜的二元体系，或包含铌酸铅镁（Pb（Mg1 / 3Nb2 / 3）O3），钛酸铅（PbTiO3））和氧化铜。还公开了一种包括内部铜电极和由介电陶瓷组合物组成的陶瓷电介质层的多层陶瓷电容器。还公开了一种容易地制造具有铜内部电极的多层陶瓷电容器的方法。该制造方法包括通过使用电介质陶瓷带和含有CuO作为其主要成分的导体糊的生胶带多层层压法来形成多层层压体; 在空气中分解除去有机粘合剂的热处理步骤（粘合剂除去工艺）; 通过在氮气和氢气的混合气体气氛中通过热处理将内部电极层中的CuO还原成铜的步骤（还原过程）; 以及在氮气氛中烧结多层层叠体的工序（烧结工序）。

14. 发明授权

US5183786A Dielectric material, and a condenser made from the same 失效
标题翻译：电介质材料及其制品
公开(公告)号：US5183786A
公开(公告)日：1993-02-02
申请号：US779439
申请日：1991-10-18
申请人： Seiji Gejima , Koji Kawakita , Suzushi Kimura , Hideyuki Okinaka , Yasuhiko Hakotani
发明人： Seiji Gejima , Koji Kawakita , Suzushi Kimura , Hideyuki Okinaka , Yasuhiko Hakotani
IPC分类号： C04B35/49 , C04B35/493 , C04B35/499 , H01B3/12 , H01G4/12
CPC分类号： H01G4/1263 , C04B35/493 , C04B35/499 , H01G4/1245
摘要： The dielectric material includes a pre-baked powder containing Pb(Mg.sub.1/3 Nb.sub.2/3)O.sub.3, BaTiO.sub.3, and BaZrO.sub.3, and lead oxides alone or lead oxides and copper oxides in combination. Thus, the dielectric material is sintered at low temperatures of 800.degree.-1000.degree. C., and makes it possible to use inexpensive electrode materials such as copper, silver, and silver-palladium alloy for the electrode. The dielectric material also makes it possible to produce a ceramic condenser or a thin condenser having a stable capacitance irrespective of changes in temperature.

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