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11. 发明授权

US5751178A Apparatus and method for shifting signal levels 失效
标题翻译：用于移位信号电平的装置和方法
公开(公告)号：US5751178A
公开(公告)日：1998-05-12
申请号：US767094
申请日：1996-12-05
申请人： Joseph Shor , Eytan Engel , Natan Baron
发明人： Joseph Shor , Eytan Engel , Natan Baron
IPC分类号： H03K17/10 , H03K19/0185 , H03K5/153
CPC分类号： H03K17/102 , H03K19/018521
摘要： The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.
摘要翻译：本发明的电子电路（100）在高（VCCH）或低（VCCL）电平处接收具有逻辑“1”的第一信号DATA（170），并在基准电平（ZERO）处接收逻辑“0”，并产生第二信号OUT（186 ）在高电平（VCCH）和参考电平（ZERO）之间，而不改变信息。电路包括串联耦合到公共输出节点（103）的第一开关（161）和第二开关（161）。第一开关（162）由从DATA，OUT或可选地从时钟信号CLK导出的控制信号（CTRL）来控制。在第二开关（162）关闭之前，第一开关（161）被断开。因此避免了同时进行的竞争（第一开关161和第二开关162）可以通过基本相等的部件来实现。

12. 发明授权

US5628026A Multi-dimensional data transfer in a data processing system and method therefor 失效
标题翻译：数据处理系统中的多维数据传输及其方法
公开(公告)号：US5628026A
公开(公告)日：1997-05-06
申请号：US349218
申请日：1994-12-05
申请人： Natan Baron , Eliezer Zand , Oded Norman , Zvika Rozenshein , Elchanan Rushinek
发明人： Natan Baron , Eliezer Zand , Oded Norman , Zvika Rozenshein , Elchanan Rushinek
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： To execute a three-dimensional DMA transfer, a transfer counter register (76), which is partitioned into three sections, is loaded with initial counter values. Each section of the counter register (76) is independently controlled by a counter (72, 73, 74). Data is transferred from consecutive generated addresses for a first predetermined number of times as determined by the value in the first section of the counter register (76). An offset value is then added to a last generated address. The process is repeated for a second predetermined number of times. Then another offset value is added to the generated address. This entire process is repeated for a given number of times as determined by the third section of the register (76). The initial counter values are reloaded into counter register (76) from a backup register (77), insuring that a DMA controller (80) is ready if a new transfer request requires the same counter values as the previous transfer.
摘要翻译：为了执行三维DMA传输，将被分割成三个部分的传送计数器寄存器（76）装入初始计数器值。计数器寄存器（76）的每个部分由计数器（72,73,74）独立地控制。数据从连续生成的地址传送，由计数器寄存器（76）的第一部分中的值确定的第一预定次数。然后将偏移值添加到最后生成的地址。该过程重复第二预定次数。然后将另一个偏移值添加到生成的地址。该整个过程由寄存器（76）的第三部分确定的给定次数重复。初始计数器值从备用寄存器（77）重新加载到计数器寄存器（76）中，确保如果新的传输请求需要与先前传输相同的计数器值，则DMA控制器（80）准备就绪。

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