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11. 发明授权

US07552283B2 Efficient memory hierarchy management 有权
标题翻译：高效的内存层次管理
公开(公告)号：US07552283B2
公开(公告)日：2009-06-23
申请号：US11336282
申请日：2006-01-20
申请人： Michael William Morrow , Thomas Andrew Sartorius
发明人： Michael William Morrow , Thomas Andrew Sartorius
IPC分类号： G06F13/00
CPC分类号： G06F9/3802 , G06F12/0848
摘要： In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.
摘要翻译：在处理器中，在执行程序之前，存在指令和程序的某些部分驻留在数据高速缓存中的情况。提供了硬件和软件技术，用于在指令高速缓存中缺少提取处理器性能之后，在数据高速缓存中取指令。如果指令高速缓存中不存在指令，则将指令提取地址作为数据提取地址发送到数据高速缓存。如果在提供的指令获取地址处存在数据高速缓存中的有效数据，则数据实际上是指令，并且将数据高速缓存条目作为指令提取并提供给处理器复合体。在指令页表中可以包括额外的位，以指示在指令高速缓存中不应该对该指令检查数据高速缓存。

12. 发明授权

US09092358B2 Memory management unit with pre-filling capability 有权
标题翻译：具有预充能力的内存管理单元
公开(公告)号：US09092358B2
公开(公告)日：2015-07-28
申请号：US13371506
申请日：2012-02-13
申请人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
发明人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
IPC分类号： G06F13/00 , G06F13/28 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译：用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数或基于访问模式动态地改变。预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

13. 发明申请

US20120226888A1 Memory Management Unit With Pre-Filling Capability 有权
标题翻译：具有预填充能力的内存管理单元
公开(公告)号：US20120226888A1
公开(公告)日：2012-09-06
申请号：US13371506
申请日：2012-02-13
申请人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
发明人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译：用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数，或者基于访问模式动态地改变。预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

14. 发明授权

US07337272B2 Method and apparatus for caching variable length instructions 有权
标题翻译：缓存可变长度指令的方法和装置
公开(公告)号：US07337272B2
公开(公告)日：2008-02-26
申请号：US11381038
申请日：2006-05-01
申请人： Michael William Morrow
发明人： Michael William Morrow
IPC分类号： G06F12/04
CPC分类号： G06F12/0886 , G06F9/30149 , G06F9/3816 , G06F9/382 , G06F12/0875
摘要： An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary position. In one or more embodiments, the cache controller duplicates instruction data for the post-boundary position in the supplemental memory, and multiplexes that copied data into cache data obtained from the pre-boundary position.
摘要翻译：指令高速缓存控制器使用补充存储器来存储对应于高速缓存边界位置的高速缓存指令数据的冗余副本，从而使得能够跟随越过该边界位置的指令的单次高速缓存访问检索。在一个或多个实施例中，高速缓存控制器复制补充存储器中的后边界位置的指令数据，并将该复制数据复用到从前置位置获得的高速缓存数据中。

15. 发明申请

US20080046702A1 Methods and Apparatus for Reducing Lookups in a Branch Target Address Cache 有权
标题翻译：用于减少分支目标地址缓存中的查找的方法和装置
公开(公告)号：US20080046702A1
公开(公告)日：2008-02-21
申请号：US11464996
申请日：2006-08-16
申请人： Michael William Morrow
发明人： Michael William Morrow
IPC分类号： G06F15/00
CPC分类号： G06F9/3844 , G06F9/3804 , G06F9/3806 , G06F9/382
摘要： A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the instruction address. The branch target address retrieved from the BTAC is stored in the I-cache. With this disclosed technique, subsequent instruction addresses are looked up in the I-cache, nonparallel to the BTAC, thus saving power by reducing needless BTAC lookups.
摘要翻译：公开了一种用于减少对分支目标地址高速缓存（BTAC）的查找的技术。在这种技术中，响应于在查询指令高速缓存（I-cache）中的指令地址的错误，从BTAC检索分支目标地址。分支目标地址与指令地址相关联。从BTAC检索的分支目标地址存储在I缓存中。利用该公开的技术，在I缓存中查找后续指令地址，不与BTAC并行，从而通过减少不必要的BTAC查找来节省功率。

16. 发明授权

US09043795B2 Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor 有权
标题翻译：非对称多处理器自适应线程调度的装置和方法
公开(公告)号：US09043795B2
公开(公告)日：2015-05-26
申请号：US12333063
申请日：2008-12-11
申请人： Michael William Morrow , Manish Garg
发明人： Michael William Morrow , Manish Garg
IPC分类号： G06F9/46 , G06F9/50 , G06F1/32
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.
摘要翻译：描述了用于减少系统能量的用于多个核上的自适应线程调度的技术。在一个实施例中，线程调度器接收与多个核相关联的漏电流信息。泄漏电流信息用于在多个核心之一上调度线程以减少系统能量消耗。还描述了传感器的片上校准。

17. 发明申请

US20080126770A1 METHODS AND APPARATUS FOR RECOGNIZING A SUBROUTINE CALL 失效
标题翻译：用于识别SUBRONTINE呼叫的方法和装置
公开(公告)号：US20080126770A1
公开(公告)日：2008-05-29
申请号：US11563943
申请日：2006-11-28
申请人： Michael William Morrow
发明人： Michael William Morrow
IPC分类号： G06F9/38
CPC分类号： G06F9/30054 , G06F9/3806
摘要： An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the next sequential address after the non-sequential change in program flow. The circuit is configured to compare the next sequential address and the contents of the register to determine whether the non-sequential change in program flow is a subroutine call.
摘要翻译：公开了一种用于识别子程序调用的装置。该装置包括电路，该电路包括用于接收寄存器的内容的第一输入端，用于接收程序流程中的非顺序改变的第二输入端和用于在程序流程中的非顺序改变之后接收下一个顺序地址的第三输入端。电路被配置为比较下一个顺序地址和寄存器的内容，以确定程序流中的非顺序改变是否是子程序调用。

18. 发明授权

US07640422B2 System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache 有权
标题翻译：用于通过将检索的BTAC地址存储到指令高速缓存中来减少分支目标地址高速缓存中的查找次数的系统
公开(公告)号：US07640422B2
公开(公告)日：2009-12-29
申请号：US11464996
申请日：2006-08-16
申请人： Michael William Morrow
发明人： Michael William Morrow
IPC分类号： G06F9/32
CPC分类号： G06F9/3844 , G06F9/3804 , G06F9/3806 , G06F9/382
摘要： A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the instruction address. The branch target address retrieved from the BTAC is stored in the I-cache. With this disclosed technique, subsequent instruction addresses are looked up in the I-cache, nonparallel to the BTAC, thus saving power by reducing needless BTAC lookups.
摘要翻译：公开了一种用于减少对分支目标地址高速缓存（BTAC）的查找的技术。在这种技术中，响应于在查询指令高速缓存（I-cache）中的指令地址的错误，从BTAC检索分支目标地址。分支目标地址与指令地址相关联。从BTAC检索的分支目标地址存储在I缓存中。利用该公开的技术，在I缓存中查找后续指令地址，不与BTAC并行，从而通过减少不必要的BTAC查找来节省功率。

19. 发明申请

US20110145542A1 Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups 审中-公开
标题翻译：用于减少翻译后备缓冲区（TLB）查找的设备，系统和方法
公开(公告)号：US20110145542A1
公开(公告)日：2011-06-16
申请号：US12638340
申请日：2009-12-15
申请人： Michael William Morrow
发明人： Michael William Morrow
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/1036 , G06F12/145 , G06F2212/1028 , G06F2212/655 , G06F2212/681 , Y02D10/13
摘要： Circuits and related systems and methods for providing virtual address translation are disclosed. In one embodiment, a circuit comprises a comparator configured to receive as an input a current virtual address and a current attribute associated with the current virtual address, and a prior physical address and a prior virtual address each associated with the current attribute. The comparator is further configured to cause the prior physical address to be provided as a current physical address if the current virtual address matches the prior virtual address associated with the current attribute. As an example, the circuit may be a TLB suppression circuit configured to reduce TLB lookups. Reducing TLB lookups can reduce power dissipation. In this regard, the circuit may also be further configured to suppress a TLB lookup to reduce power dissipation when the current virtual address matches the prior virtual address.
摘要翻译：公开了用于提供虚拟地址转换的电路和相关系统和方法。在一个实施例中，电路包括比较器，其被配置为接收与当前虚拟地址相关联的当前虚拟地址和当前属性作为输入，以及与当前属性相关联的先前物理地址和先前虚拟地址。比较器还被配置为如果当前虚拟地址与当前属性相关联的先前虚拟地址匹配，则将先前的物理地址提供为当前物理地址。作为示例，电路可以是被配置为减少TLB查找的TLB抑制电路。减少TLB查找可以降低功耗。在这方面，电路还可以被配置为当当前虚拟地址与先前的虚拟地址匹配时，抑制TLB查找以减少功耗。

20. 发明申请

US20100153954A1 Apparatus and Methods for Adaptive Thread Scheduling on Asymmetric Multiprocessor 有权
标题翻译：不对称多处理器上自适应线程调度的设备与方法
公开(公告)号：US20100153954A1
公开(公告)日：2010-06-17
申请号：US12333063
申请日：2008-12-11
申请人： Michael William Morrow , Manish Garg
发明人： Michael William Morrow , Manish Garg
IPC分类号： G06F9/46
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.
摘要翻译：描述了用于减少系统能量的用于多个核上的自适应线程调度的技术。在一个实施例中，线程调度器接收与多个核相关联的漏电流信息。泄漏电流信息用于在多个核心之一上调度线程以减少系统能量消耗。还描述了传感器的片上校准。

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