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11. 发明申请

US20080065810A1 ASSISTED TRACE FACILITY TO IMPROVE CPU CACHE PERFORMANCE 失效
标题翻译：辅助跟踪功能来提高CPU高速缓存的性能
公开(公告)号：US20080065810A1
公开(公告)日：2008-03-13
申请号：US11530393
申请日：2006-09-08
申请人： Carol Spanel , Andrew Dale Walls
发明人： Carol Spanel , Andrew Dale Walls
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F11/348 , G06F11/3471
摘要： A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.
摘要翻译：用于在保存缓存资源的同时记录跟踪数据的系统和方法包括生成跟踪数据并创建包含跟踪数据的高速缓存行。为缓存线分配一个标签，该标签对应于指定用于处理跟踪数据的中间地址。高速缓存线还包括在其中嵌入存储跟踪数据的存储器中的实际地址，其可以包括实际地址或虚拟地址。高速缓存行可以在中间地址处被接收并被解析以读取实际地址。然后可以将跟踪数据写入与实际地址相对应的存储器中的位置。通过路由跟踪数据通过指定的中间地址，CPU缓存可以保存为其他更重要或更频繁访问的数据。

12. 发明授权

US07085859B2 Method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected 失效
标题翻译：用于从主机总线适配器自动呈现状态直到检测到错误的方法，装置和程序存储装置
公开(公告)号：US07085859B2
公开(公告)日：2006-08-01
申请号：US10437554
申请日：2003-05-14
申请人： James Chien-Chiung Chen , Carol Spanel , Andrew Dale Walls , Lih-Chung Kuo
发明人： James Chien-Chiung Chen , Carol Spanel , Andrew Dale Walls , Lih-Chung Kuo
IPC分类号： G06F3/00 , G06F13/00 , G06F13/14
CPC分类号： G06F13/385
摘要： A method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected is provided. Data is transmitted between the host bus adapter and a host. The host performs data transmission validation and determines whether data transmission was successful. The host bus adapter automatically sends status information when data transmission was successful, else the host bus adapter waits for status type identification from the host for transmission of data.
摘要翻译：提供一种用于自动呈现来自主机总线适配器的状态直到检测到错误的方法，装置和程序存储装置。数据在主机总线适配器和主机之间传输。主机执行数据传输验证，并确定数据传输是否成功。主机总线适配器在数据传输成功时自动发送状态信息，否则主机总线适配器等待来自主机的数据传输的状态类型识别。

13. 发明申请

US20080263391A1 Apparatus, System, and Method For Adapter Card Failover 审中-公开
标题翻译：用于适配器卡故障转移的设备，系统和方法
公开(公告)号：US20080263391A1
公开(公告)日：2008-10-23
申请号：US11738150
申请日：2007-04-20
申请人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F11/07
CPC分类号： G06F11/2038 , G06F11/2033 , G06F11/2046
摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
摘要翻译：公开了用于适配器卡故障切换的装置，系统和方法。开关模块通过作为所有者处理器的第一端口将第一处理器复合体连接到适配器卡。所有者处理器复合体管理适配器卡，但第二个端口除外，并从适配器卡接收错误消息。交换机模块通过第二端口进一步将第二处理器复合体连接到适配器卡作为非所有者处理器复合体。非所有者处理器复合体管理第二个端口。检测模块检测第一处理器复杂的故障。设置模块修改交换机模块以将所有者处理器复杂化，将第二处理器复合体逻辑连接到适配器卡，并根据检测到故障从逻辑上断开第一个处理器复合体与适配器卡的连接。

14. 发明授权

US07073030B2 Method and apparatus providing non level one information caching using prefetch to increase a hit ratio 失效
公开(公告)号：US07073030B2
公开(公告)日：2006-07-04
申请号：US10153966
申请日：2002-05-22
申请人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0862 , G06F12/0897 , G06F2212/6024
摘要： A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.

15. 发明授权

US06519666B1 Arbitration scheme for optimal performance 失效
标题翻译：最优性能的仲裁方案
公开(公告)号：US06519666B1
公开(公告)日：2003-02-11
申请号：US09412990
申请日：1999-10-05
申请人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13368
CPC分类号： G06F13/362
摘要： A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than the others and including a peripheral device. Each master may request control of the shared bus and is adapted to perform short transfers and long burst transfers on the shared bus between a resource and the master. A shared bus arbiter is utilized for dynamically determining the highest priority request between a number of shared bus requests, and granting control of the shared bus to the highest priority requesting bus master. The arbiter utilizes a three-level priority hierarchy arbitration scheme where the highest priority level is given to short message transfer requests on the higher-priority system resources, the intermediate priority level is given to short message transfer requests on the lower-priority system resources, if there are no outstanding higher priority level requests, and the lowest priority level is given for long burst transfers, if there are no outstanding short message transfer requests.
摘要翻译：提供了一种用于数据通信系统的共享总线仲裁方案，其中共享总线连接到多个总线主机和资源，一些资源具有比其他资源更高的优先级，并且包括外围设备。每个主机可以请求对共享总线的控制，并且适于在资源和主机之间的共享总线上执行短传输和长突发传输。共享总线仲裁器用于动态地确定多个共享总线请求之间的最高优先级请求，以及授予对最高优先级请求总线主机的共享总线的控制。仲裁器采用三级优先级分级仲裁方案，其中优先级较高的优先级优先级较高优先级系统资源上的短消息传输请求，中间优先权级别给予低优先级系统资源上的短消息传输请求，如果没有突出的较高优先级请求，并且对于长突发传输给出最低优先级，则如果没有未完成的短消息传送请求。

16. 发明授权

US07562284B2 Apparatus, system, and method for mandatory end to end integrity checking in a storage system 有权
标题翻译：用于存储系统中强制性端对端完整性检查的装置，系统和方法
公开(公告)号：US07562284B2
公开(公告)日：2009-07-14
申请号：US11212208
申请日：2005-08-26
申请人： Michael Thomas Benhase , Michael John Palmer , William Garrett Verdoorn, Jr. , Andrew Dale Walls
发明人： Michael Thomas Benhase , Michael John Palmer , William Garrett Verdoorn, Jr. , Andrew Dale Walls
IPC分类号： H03M13/00
CPC分类号： G06F11/08
摘要： An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus includes a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system includes a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.
摘要翻译：公开了用于强制性的端对端完整性检查的装置，系统和方法。所述装置包括：配置为监视来自源的数据并且验证与标准的完整性信息兼容性的兼容性模块，以及被配置为用源包含附加完整性信息的数据的完整性模块。该系统包括被配置为通过网络发送数据的源，被配置为通过网络接收数据的目标，该设备，主存储器模块，存储控制器和存储设备。该方法包括监视来自源的数据，验证与标准的完整性信息兼容性，以及使用附加的完整性信息来包括来自源的数据。

17. 发明授权

US07596651B2 Multi-character adapter card 失效
标题翻译：多字符适配卡
公开(公告)号：US07596651B2
公开(公告)日：2009-09-29
申请号：US11754821
申请日：2007-05-29
申请人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F9/06
CPC分类号： G06F13/385
摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.
摘要翻译：根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。逻辑芯片连接到电路板以向适配器卡提供功能。一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

18. 发明授权

US07472218B2 Assisted trace facility to improve CPU cache performance 失效
标题翻译：辅助跟踪工具来提高CPU缓存的性能
公开(公告)号：US07472218B2
公开(公告)日：2008-12-30
申请号：US11530393
申请日：2006-09-08
申请人： Carol Spanel , Andrew Dale Walls
发明人： Carol Spanel , Andrew Dale Walls
IPC分类号： G06F12/00
CPC分类号： G06F11/348 , G06F11/3471
摘要： A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.
摘要翻译：用于在保存缓存资源的同时记录跟踪数据的系统和方法包括生成跟踪数据并创建包含跟踪数据的高速缓存行。为缓存线分配一个标签，该标签对应于指定用于处理跟踪数据的中间地址。高速缓存线还包括在其中嵌入存储跟踪数据的存储器中的实际地址，其可以包括实际地址或虚拟地址。高速缓存行可以在中间地址处被接收并被解析以读取实际地址。然后可以将跟踪数据写入与实际地址相对应的存储器中的位置。通过路由跟踪数据通过指定的中间地址，CPU缓存可以保存为其他更重要或更频繁访问的数据。

19. 发明申请

US20080301530A1 APPARATUS AND METHOD FOR DISTINGUISHING TEMPORARY AND PERMANENT ERRORS IN MEMORY MODULES 失效
标题翻译：用于记忆模块中临时和永久错误的设备和方法
公开(公告)号：US20080301530A1
公开(公告)日：2008-12-04
申请号：US11757221
申请日：2007-06-01
申请人： Carol Spanel , Andrew Dale Walls
发明人： Carol Spanel , Andrew Dale Walls
IPC分类号： G11C29/52
CPC分类号： G11C29/52 , G06F11/1012 , G11C5/04 , G11C29/44 , G11C2029/0409 , G11C2029/0411
摘要： An apparatus and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.
摘要翻译：公开了用于区分存储器中的可校正位错误的装置和方法。响应于READ操作，位错误检测模块检测存储器中的可校正位错误。使用纠错码可纠正位错误。在正常操作期间产生READ操作。比较模块将错误位置指示器与存储的错误位置指示器进行比较。错误位置指示符包括可纠正位错误的存储位置。存储的错误位置指示符对应于先前存储的可纠错位错误的错误位置指示符。如果比较模块确定错误位置指示符与存储的错误位置指示符不同，则存储模块存储错误位置指示符。如果比较模块确定错误位置指示符与存储的错误位置指示符匹配，则错误计数器模块增加与错误位置指示符相对应的错误计数器。

20. 发明申请

US20080263255A1 Apparatus, System, and Method For Adapter Card Failover 有权
公开(公告)号：US20080263255A1
公开(公告)日：2008-10-23
申请号：US11738142
申请日：2007-04-20
申请人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13/36
CPC分类号： G06F11/2038 , G06F11/2033 , G06F11/2046
摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

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