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11. 发明授权

US08726124B2 Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers 有权
标题翻译：通过分布式时间复用线性反馈移位寄存器生成循环冗余校验
公开(公告)号：US08726124B2
公开(公告)日：2014-05-13
申请号：US13553583
申请日：2012-07-19
申请人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
发明人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/6502 , H03M13/6575
摘要： Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.
摘要翻译：使用改进的线性反馈移位寄存器（LFSR）电路有效地计算循环冗余校验（CRC）值。 CRC值生成被分成两个子计算，然后将它们组合以形成最终的CRC值。可编程XOR引擎通过表查找执行逻辑功能，而不是通过随机逻辑电路执行逻辑功能。使用单个共享LFSR电路执行LCRC和ECRC计算。多个链路共享相同的CRC值生成器。本发明的一个优点是使用相对于常规电路设计的较小和较少的LFSR电路产生CRC值。结果，利用所公开的技术的CRC值发生器消耗了较少的集成电路的表面积并且消耗较少的功率，导致较冷的操作。

12. 发明授权

US08738990B2 Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers 有权
公开(公告)号：US08738990B2
公开(公告)日：2014-05-27
申请号：US13553619
申请日：2012-07-19
申请人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
发明人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
IPC分类号： H03M13/00
CPC分类号： H03M13/6502 , H03M13/091 , H03M13/6575 , H04L1/0061
摘要： Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

13. 发明授权

US08812892B1 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection 有权
标题翻译：硬件WCK2CK培训引擎采用meta-EDC扫描和可调精确的投票算法进行时钟相位检测
公开(公告)号：US08812892B1
公开(公告)日：2014-08-19
申请号：US12650242
申请日：2009-12-30
申请人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
发明人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/10
摘要： One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
摘要翻译：本发明的一个实施例提出了一种用于执行高性能时钟训练的技术。执行一个时钟训练扫描操作以确定相对于命令时钟的两个写入时钟的相位关系。生成相位关系以满足两种不同客户端设备（如GDDR5 DRAM组件）的时序要求。执行第二时钟训练扫描操作以更好地对准在客户端设备上操作的本地时钟。在第二次时钟训练扫描期间保持投票记录，以在时钟训练扫描的每个步骤记录相位协议。然后，投票计数确定是否应将本地时钟之一反转以更好地对准两个本地时钟。

14. 发明申请

US20140026021A1 CYCLIC REDUNDANCY CHECK GENERATION VIA DISTRIBUTED TIME MULTIPLEXED LINEAR FEEDBACK SHIFT REGISTERS 有权
标题翻译：循环冗余通过分布式时间检查多路复用线性反馈移位寄存器
公开(公告)号：US20140026021A1
公开(公告)日：2014-01-23
申请号：US13553583
申请日：2012-07-19
申请人： Eric Lyell Hill , Richard L. Schober, JR. , Hungse Cha
发明人： Eric Lyell Hill , Richard L. Schober, JR. , Hungse Cha
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/6502 , H03M13/6575
摘要： Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.
摘要翻译：使用改进的线性反馈移位寄存器（LFSR）电路有效地计算循环冗余校验（CRC）值。 CRC值生成被分成两个子计算，然后将它们组合以形成最终的CRC值。可编程XOR引擎通过表查找执行逻辑功能，而不是通过随机逻辑电路执行逻辑功能。使用单个共享LFSR电路执行LCRC和ECRC计算。多个链路共享相同的CRC值生成器。本发明的一个优点是使用相对于常规电路设计的较小和较少的LFSR电路产生CRC值。结果，利用所公开的技术的CRC值发生器消耗了较少的集成电路的表面积并且消耗较少的功率，导致较冷的操作。

15. 发明授权

US08489911B1 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection 有权
标题翻译：硬件WCK2CK培训引擎采用meta-EDC扫描和可调精确的投票算法进行时钟相位检测
公开(公告)号：US08489911B1
公开(公告)日：2013-07-16
申请号：US12650281
申请日：2009-12-30
申请人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
发明人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/10
摘要： One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
摘要翻译：本发明的一个实施例提出了一种用于执行高性能时钟训练的技术。执行一个时钟训练扫描操作以确定相对于命令时钟的两个写入时钟的相位关系。生成相位关系以满足两种不同客户端设备（如GDDR5 DRAM组件）的时序要求。执行第二时钟训练扫描操作以更好地对准在客户端设备上操作的本地时钟。在第二次时钟训练扫描期间保持投票记录，以在时钟训练扫描的每个步骤记录相位协议。然后，投票计数确定是否应将本地时钟之一反转以更好地对准两个本地时钟。

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