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11. 发明申请

US20070058408A1 Semiconductor memory array with serial control/address bus 有权
标题翻译：具有串行控制/地址总线的半导体存储器阵列
公开(公告)号：US20070058408A1
公开(公告)日：2007-03-15
申请号：US11226447
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
发明人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。

12. 发明申请

US20100074038A1 Memory Dies for Flexible Use and Method for Configuring Memory Dies 有权
标题翻译：用于灵活使用的内存模式和配置内存模块的方法
公开(公告)号：US20100074038A1
公开(公告)日：2010-03-25
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10 , H01L21/66 , H01L23/538
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

13. 发明授权

US07844798B2 Command protocol for integrated circuits 有权
标题翻译：集成电路命令协议
公开(公告)号：US07844798B2
公开(公告)日：2010-11-30
申请号：US11955659
申请日：2007-12-13
申请人： Andreas Gärtner , Georg Braun , Maurizio Skerlj , Johannes Stecker
发明人： Andreas Gärtner , Georg Braun , Maurizio Skerlj , Johannes Stecker
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C8/12 , G11C2207/2227 , Y02D10/14 , Y02D10/171
摘要： A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that provides additional information about the operation to be performed. The attributes portion of the command is supplied to the integrated circuit with a delay relative to the instruction portion of the command. The integrated circuit selectively enables circuitry for processing the attributes portion if the integrated circuit determines from the received instruction portion that the command also includes an attributes portion. The delay between the two portions of the command provides sufficient time for the integrated circuit to enable the attributes processing circuitry, which, in a default state, can be disabled during an active mode of the integrated circuit to save power.
摘要翻译：一种操作集成电路的方法包括向集成电路提供命令的指令部分，以指定要由集成电路执行的操作。至少一些类型的命令还包括提供关于要执行的操作的附加信息的属性部分。命令的属性部分相对于命令的指令部分延迟地提供给集成电路。如果集成电路从接收到的指令部分确定该命令还包括属性部分，则集成电路选择性地启用用于处理属性部分的电路。该命令的两个部分之间的延迟为集成电路提供了足够的时间，使得能够在集成电路的活动模式期间在默认状态下禁用属性处理电路以节省功率。

14. 发明授权

US07796446B2 Memory dies for flexible use and method for configuring memory dies 有权
标题翻译：用于灵活使用的存储器模块和用于配置存储器管芯的方法
公开(公告)号：US07796446B2
公开(公告)日：2010-09-14
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

15. 发明授权

US07376802B2 Memory arrangement 失效
标题翻译：内存安排
公开(公告)号：US07376802B2
公开(公告)日：2008-05-20
申请号：US10850382
申请日：2004-05-21
申请人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
发明人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译：本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。

16. 发明申请

US20060092715A1 Circuit 有权
标题翻译：电路
公开(公告)号：US20060092715A1
公开(公告)日：2006-05-04
申请号：US11099222
申请日：2005-04-05
申请人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
发明人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
IPC分类号： G11C7/10
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译：电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。此外，电路还具有用于基于参考电平来评估信号的装置。

17. 发明申请

US20060062039A1 DQS signaling in DDR-III memory systems without preamble 有权
标题翻译：没有前导码的DDR-III存储器系统中的DQS信号
公开(公告)号：US20060062039A1
公开(公告)日：2006-03-23
申请号：US11214067
申请日：2005-08-30
申请人： Hermann Ruckerbauer , Georg Braun , Amir Motamedi
发明人： Hermann Ruckerbauer , Georg Braun , Amir Motamedi
IPC分类号： G11C5/06
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.
摘要翻译：特别是作为DDR-III存储器芯片通信电路的一部分的数据传输系统执行无前导码的数据传输操作。该数据传输系统包括至少一条具有可接通和关断的管芯端接的数据线，并且数据线的芯片端连接到正极或接地或负极的电源电压线通过上拉或下拉电阻。或者，数据传输系统的操作是在相应的运行状态下接通的终端电路不被打开的定时，直到被激活的驱动程序被激活为止。

18. 发明申请

US20050038966A1 Memory arrangement 失效
标题翻译：内存安排
公开(公告)号：US20050038966A1
公开(公告)日：2005-02-17
申请号：US10850382
申请日：2004-05-21
申请人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
发明人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
IPC分类号： G06F13/16 , G11C7/10 , G06F12/00
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译：本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。

19. 发明授权

US07447805B2 Buffer chip and method for controlling one or more memory arrangements 有权
标题翻译：用于控制一个或多个存储器布置的缓冲器芯片和方法
公开(公告)号：US07447805B2
公开(公告)日：2008-11-04
申请号：US10792408
申请日：2004-03-03
申请人： Georg Braun , Hermann Ruckerbauer
发明人： Georg Braun , Hermann Ruckerbauer
IPC分类号： G06F13/00 , G06F13/38 , G06F3/00 , G06F5/00 , G06F12/00
CPC分类号： G06F13/1673 , G06F12/0215 , G06F12/0862 , G06F2212/6022
摘要： A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.
摘要翻译：一种具有第一数据接口的缓冲器芯片，用于接收要写入的数据项，并且用于发送已经被读取的数据项，具有用于并行化所接收的数据项的转换单元，并且用于串行化要发送的数据项，具有用于经由存储器数据总线将并行化数据项写入存储器装置的第二数据接口，以及用于经由存储器数据总线接收从存储器装置读取的数据项; 具有用于缓冲存储要写入的数据项的写缓冲存储器，具有按顺序具有控制单元，在接收到要经由第一数据接口写入的数据项以符合写命令之后，中断在随后的读取命令时，经由第二数据接口从写缓冲存储器写入的数据。

20. 发明授权

US07362622B2 System for determining a reference level and evaluating a signal on the basis of the reference level 有权
标题翻译：用于确定参考电平并基于参考电平评估信号的系统
公开(公告)号：US07362622B2
公开(公告)日：2008-04-22
申请号：US11099222
申请日：2005-04-05
申请人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
发明人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
IPC分类号： G11C7/10 , G11C7/20 , G06F9/00
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译：电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。此外，电路还具有用于基于参考电平来评估信号的装置。

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